公开(公告)号：EP1821587A3

公开(公告)日：2009-07-01

申请号：EP07002961.6

申请日：2007-02-12

Applicant: DENSO CORPORATION

Inventor： Ito, Atsushi ,  Honda, Takayoshi ,  Mikura, Hidehiro ,  Tsuruzawa, Tadashi ,  Sakuta, Takuya

IPC: H05K3/34

CPC classification number: H05K3/3421 ,  H05K1/111 ,  H05K3/3426 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09709 ,  H05K2201/10189 ,  H05K2201/10787 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounting structure includes a board (110) and an electronic component (130) mounted on a front surface of the board (110). The board (110) includes lands (112). The electronic component (130) includes a body (131) and terminals (132) extending from the body (131). Each terminal (132) is electrically connected to a corresponding one of the lands (112) of the board (110). The terminal (132) has a first terminal portion (132a) extending along the front surface of the board (110) and a second terminal portion (132b) extending toward the front surface of the board (110). Each land (112) includes a land portion electrically soldered to the first terminal portion (132a) and a blind hole (111) for receiving the second terminal portion (132b). The first terminal portion (132a) is soldered to the land portion in a reflow process under the condition that the second terminal portion (132b) is inserted in the blind hole (111).

Abstract translation: 电子部件安装结构包括安装在板（110）的前表面上的板（110）和电子部件（130）。 板（110）包括平台（112）。 电子部件（130）包括主体（131）和从主体（131）延伸的端子（132）。 每个端子（132）电连接到板（110）的相应的一个焊盘（112）。 端子（132）具有沿着板（110）的前表面延伸的第一端子部分（132a）和朝向板（110）的前表面延伸的第二端子部分（132b）。 每个平台（112）包括电焊接到第一端子部分（132a）的接地部分和用于接收第二端子部分（132b）的盲孔（111）。 在第二端子部分（132b）插入盲孔（111）的条件下，第一端子部分（132a）以回流工艺焊接到焊盘部分。

公开(公告)号：EP1542520A4

公开(公告)日：2008-12-03

申请号：EP03792769

申请日：2003-08-21

Applicant: JSR CORP

Inventor： OHTA MASARU ,  INOMATA KATSUMI ,  IWANAGA SHINICHIRO

IPC: G03F7/11 ,  G03F7/40 ,  G03F7/42 ,  H01L21/60 ,  H01L23/12 ,  H05K3/28 ,  H05K3/34

CPC classification number: H01L24/12 ,  H01L24/02 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/10126 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01009 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H05K3/28 ,  H05K3/3473 ,  H05K3/3478 ,  H05K3/3484 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0577 ,  H05K2203/0793

Abstract: A method for forming a bump on an electrode pad characterized in that at least the following steps (a)-(d) are conducted on a wiring substrate which is composed of a base and a plurality of electrode pads: (a) a step wherein a double-layered film composed of a lower layer made of an alkali-soluble, radiation-nonsensitive resin composition and an upper layer made of a negative, radiation-sensitive resin composition is formed on the wiring substrate, and then an aperture pattern is formed in a corresponding position of the electrode pad; (b) a step wherein a low-melting metal is introduced into the aperture pattern; (c) a step wherein the low-melting metal is reflowed by conducting a press or a heat treatment so as to from a bump, and (d) a step wherein the double-layered film is removed from the substrate. By using the double-layered film having different characteristics, the high-resolution property and the easy-release property become compatible.

公开(公告)号：EP1936677A2

公开(公告)日：2008-06-25

申请号：EP07024790.3

申请日：2007-12-20

Applicant: TDK Corporation

Inventor： Kawabata, Kenichi ,  Nagase, Kenji

IPC: H01L21/60 ,  H01L23/538

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch.
In a semiconductor-embedded substrate (1), a conductive pattern (13) is formed on both sides of a core substrate (11) and a semiconductor device (14) is placed in a resin layer (16) stacked over the core substrate. The resin layer has via-holes (19a,19b) so that the conductive pattern and a bump (14p) of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions (23a,23b) whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

Abstract translation: 本发明提供一种布线结构等，其可以将布线层完全连接到待布线的本体，同时保持两个相邻布线层之间的绝缘，并且由于间距变窄而实现高密度封装。 在半导体嵌入式基板（1）中，在芯基板（11）的两面形成导电图案（13），将半导体装置（14）配置在层叠在芯基板上的树脂层（16）中。 树脂层具有通孔（19a，19b），使得导电图案和半导体器件的凸块（14p）从树脂层突出。 在通孔内部，凸块和导电图案分别连接到横截面积已经朝向通孔底部增加的通孔电极部分（23a，23b）。 在通孔电极部分和通孔的内壁的上部之间限定空隙。

公开(公告)号：EP1895586A2

公开(公告)日：2008-03-05

申请号：EP07122502.3

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： The designation of the inventor has not yet been filed

IPC: H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: The invention relates to a package board having a core board (30) on each surface of which a plurality of conductor circuits are formed with an interlaminar resin insulating layer therebetween, wherein a plurality of soldering pads (75U,75D) are formed on the IC chip mounted side surface, as well as on the other side surface to be connected to another board, so that said soldering pads (75D) on the other side surface are larger than those on said IC chip side surface of said package board, and a dummy pattern (58M) is formed between conductor circuit patterns formed on said IC chip mounted side surface of said core board.

Abstract translation: 本发明涉及一种封装板，其具有在其表面上的多个导体电路在其间形成有层间树脂绝缘层的芯板（30），其中在IC上形成多个焊盘（75U，75D） 芯片安装侧面以及与另一个板连接的另一侧表面，使得另一侧表面上的所述焊盘（75D）大于所述封装板的所述IC芯片侧表面上的焊盘（75D），并且 在形成在所述芯板的所述IC芯片安装侧表面上的导体电路图案之间形成虚设图案（58M）。

公开(公告)号：EP1802186A3

公开(公告)日：2007-09-19

申请号：EP07006712.9

申请日：1997-09-16

Applicant: IBIDEN CO., LTD.

Inventor： Ono, Yoshitaka ,  Goto, Akihiko ,  Niki, Ayao ,  Asai, Motoo

IPC: H05K3/24 ,  H05K3/34 ,  H05K3/28 ,  H05K3/38

CPC classification number: H05K3/244 ,  G03F7/032 ,  G03F7/0388 ,  H05K1/112 ,  H05K3/184 ,  H05K3/28 ,  H05K3/287 ,  H05K3/3457 ,  H05K3/384 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/0307 ,  H05K2203/0392 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T428/24917

Abstract: The present invention refers to a printed circuit board comprising a wiring substrate provided with conductor circuits (5), a solder resist layer (14) formed on the surface of the substrate, and a solder body (17) fed onto a pad as a part of the conductor circuit (5) exposed from an opening portion formed in the solder resist layer (14), in which the surface of the pad is rendered into an electrically conductive roughened layer (11), and a metal layer (15,16) having a non-oxidizing metal (16) on at least a surface-thereof is formed on a surface of the pad exposed from the opening portion, and the solder (17) is supported on the pad through the metal layer (15,16).

公开(公告)号：EP1635624A3

公开(公告)日：2007-08-01

申请号：EP05018498.5

申请日：2005-08-25

Applicant: NITTO DENKO CORPORATION

Inventor： Kanagawa, Hitoki ,  Ohsawa, Tetsuya ,  Ooyabu, Yasunari

IPC: H05K1/11 ,  H05K3/34 ,  G11B5/48

CPC classification number: G11B5/4853 ,  G11B5/4846 ,  G11B5/486 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/111 ,  H05K3/3452 ,  H05K3/3478 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2203/041 ,  Y02P70/611 ,  H01L2924/00

Abstract: A wired circuit board having terminals that can ensure large electrical connection areas while preventing shorting of adjacent terminals, to ensure that the terminals are electrically connected with external terminals through molten metal. An insulating base layer 3 is formed on a supporting board 2 so that insulating concave portions 13 are formed at portions thereof where external connecting terminals 8 are to be formed. A conductive pattern 4 is formed on the insulating base layer 3 so that a number of lines of wire 4a, 4b, 4c, 4d, the magnetic head connecting terminals 7, and the external connecting portions 8 are integrally formed, and conductive concave portions 9 are formed in the external connecting terminals 8. Thereafter, an insulating cover layer 10 is formed on the insulating base layer 3 so that the magnetic head connecting terminals 7 and the external connecting terminals 8 are exposed from the insulating cover layer 10. In the suspension board with circuit 1 thus formed, when the external connecting terminals 8 are connected with connecting terminals of a read/write substrate via the solder balls 21, reliable connection therebetween can be ensured.

Abstract translation: 一种布线电路板，其具有能够确保较大电连接面积同时防止相邻端子短路的端子，以确保端子通过熔融金属与外部端子电连接。 在支承基板2上形成基底绝缘层3，在形成外部连接端子8的部分形成绝缘性的凹部13。 导电图案4形成在基底绝缘层3上，使得多根导线4a，4b，4c，4d，磁头连接端子7和外部连接部8一体地形成，并且导电凹部9 形成在外部连接端子8中。此后，在基底绝缘层3上形成绝缘覆盖层10，使得磁头连接端子7和外部连接端子8从绝缘覆盖层10露出。在悬架 当外部连接端子8经由焊球21与读/写基板的连接端子连接时，可以确保其间可靠的连接。

公开(公告)号：EP1796445A2

公开(公告)日：2007-06-13

申请号：EP07002566.3

申请日：1997-06-12

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo ,  Kawamura, Yoichiro

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H01L23/498 ,  H01L23/538

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/099 ,  H05K2201/10734 ,  H05K2203/0156 ,  H05K2203/0338 ,  H05K2203/0405 ,  H05K2203/043 ,  H01L2924/00

Abstract: A multilayer printed circuit board comprising a core substrate, multilayer wiring layers formed on the substrate by alternately laminating an interlaminar insulating layer and conductor pattern and a group of solder pads having solder bumps planarly arranged on an outermost surface of the multilayer wiring layers, characterized in that first, the solder pads located from first row to fifth row from an outer position of the solder pad group are constructed with flat pads connected to conductor patterns located on the outermost surface and having solder bumps formed on surfaces of the pads, while the solder pad group other than these solder pads are constructed with viaholes connected to a flat innerlayer pad group located in an inner layer and having solder bumps formed in recess portions of the viaholes and, second, the solder pads located from first row to fifth row from an outer position of the innerlayer pad group are constructed with flat pads connected to conductor patterns in the same layer as the innerlayer pad group, while the innerlayer pad group other than these pads are constituted with flat pads connected to a further innerlayer flat pad group located inward the above innerlayer through viaholes and, third, the layer having the structure of the above second feature is at least one layer.

Abstract translation: 一种多层印刷电路板，包括芯基板，通过交替层叠层间绝缘层和导体图案而形成在所述基板上的多层布线层和具有平面布置在所述多层布线层的最外表面上的焊料凸块的一组焊料焊盘，其特征在于， 首先，从焊料焊盘组的外部位置开始位于第一行至第五行的焊盘构造为连接到位于最外表面上并且在焊盘表面上形成焊料凸块的导体图案的平坦焊盘，而焊料 除了这些焊盘之外的焊盘组构造有连接到位于内层中的平坦内层焊盘组的通孔，并且具有形成在通孔的凹部中的焊料凸块，以及第二焊盘从第一行至第五行位于 内层焊盘组的外部位置由连接到导体图案中的平坦焊盘构成 与内层垫组相同，而除了这些垫之外的内层垫组由通过通孔连接到位于上述内层的另一内层平垫组的平垫构成，第三，具有上述第二结构的层 功能至少有一层。

公开(公告)号：EP1793419A1

公开(公告)日：2007-06-06

申请号：EP05077757.2

申请日：2005-12-02

Applicant: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO

Inventor： Puik, Erik Christian Nicolaas ,  Smulders, Edwin Johannes Theodorus

IPC: H01L21/60 ,  H05K3/00 ,  H05K3/32 ,  H05K3/34

CPC classification number: H05K3/321 ,  B81C99/002 ,  B81C2203/032 ,  H01L21/6835 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2924/15312 ,  H05K3/28 ,  H05K2201/09472 ,  H05K2201/10704 ,  H05K2203/0178 ,  H05K2203/1105 ,  H05K2203/1121 ,  H05K2203/1446

Abstract: Method and system for moving a frozen adhesive particle towards a target body, comprising launching means (13) which are arranged to launch the particle (2) in its frozen form towards the target body (3,4) via a movement path (14) through a gap (15) between the launching means and the target body. The medium in the gap may have a temperature above the adhesive particle's melting temperature. The launching means may be arranged to launch the particle at a high speed. The launching means and the target body may have a geometry causing that the movement path is substantially vertical or substantially horizontal.

Abstract translation: 用于将冷冻粘合剂颗粒朝向目标体移动的方法和系统，包括发射装置（13），其被布置成经由移动路径（14）将其冻结形式的颗粒（2）朝向目标体（3,4） 通过发射装置和目标体之间的间隙（15）。 间隙中的介质可能具有高于粘合剂颗粒的熔融温度的温度。 发射装置可以被布置成以高速度发射颗粒。 发射装置和目标体可以具有导致移动路径基本上垂直或基本水平的几何形状。

公开(公告)号：EP1030365A4

公开(公告)日：2007-05-09

申请号：EP98944278

申请日：1998-09-28

Applicant: IBIDEN CO LTD

Inventor： ASAI MOTOO ,  MORI YOJI

IPC: H05K3/46 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Conventionally the solder pads on the IC chip side surface (upper surface) of a package substrate are small (133-170 νm diameter) and occupy a relatively small metallic part, while the solder pads on the surface (lower surface) of a mother board are large (600 νm diameter) and occupy a large metallic part. According to the invention, the metallic part on the IC chip side of the package substrate is increased by forming a dummy pattern (58M) between the conductor circuits (58U), (58U) forming signal lines on the IC chip side of the package substrate, and the ratio of the metallic part of the IC chip side to that of the mother board side is adjusted. The package substrate does not warp during the manufacturing process and during the use thereof.

公开(公告)号：EP1659841A2

公开(公告)日：2006-05-24

申请号：EP06003039.2

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： Tsukada, Kiyotaka ,  Takada, Masaru ,  Chihara, Kenji

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser is provided. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.

Abstract translation: 提供一种印刷电路板及其制造方法，其在形成具有激光的盲孔时有利于形成上表面图案并防止下表面金属箔被损坏。 绝缘基板（5）的下表面和上表面分别涂覆有下表面金属箔（220）和上表面金属箔（210），其厚度小于下表面金属箔的厚度 （220）。 接下来，在上表面金属箔的与绝缘基板的盲通孔形成部（35）对应的位置形成开口（213）。 通过开口（213）向盲通孔形成部分（35）发射激光（8），形成其底部为下表面金属箔的盲通孔（3）。 然后，将金属镀膜（23）施加到盲孔（3）的壁上，通过蚀刻形成上表面图案（21）和下表面图案（22）。