公开(公告)号：EP1943887A1

公开(公告)日：2008-07-16

申请号：EP06814781.8

申请日：2006-09-15

Applicant: Finisar Corporation

Inventor： ICE, Donald, A. ,  NELSON, Stephen, T. ,  DOUMA, Darin James

IPC: H05K1/00

CPC classification number: H05K3/3405 ,  G02B6/4201 ,  G02B6/4245 ,  G02B6/4246 ,  G02B6/4255 ,  G02B6/4292 ,  H01R13/6315 ,  H05K1/0278 ,  H05K1/141 ,  H05K3/202 ,  H05K3/3447 ,  H05K2201/0394 ,  H05K2201/049 ,  H05K2201/09118 ,  H05K2201/10121 ,  H05K2201/10446 ,  H05K2201/10757 ,  H05K2201/10924 ,  H05K2203/302

Abstract: An optical transceiver module having aplurality of optical subassemblies (1001 and a printed circuit board (150) is disclosed The transceiver module includes lead frame connectors (12,22) for connecting the optical subassemblies to the printed circuit board The lead frame connectors include a stamped and bent conductive lead structure (30) that is encased in an insert injection molded plastic casing (32) The plastic casing provides electrical insulation for the conductors in the lead frame as well as mechanical support for the finished component The lead frame connectors connect to the leads associated with the optical subassemblies and are surface mounte onto the printed circuit board to establish connectivity betwedn the optical subassembly and the printed circuit board The lead frame assemblies are generally more reliable and less expensive than using flexible printed circuit board structures to establish electrical connectivity between optical subassemblies and transceiver printed circuit boards

Abstract translation: 公开了一种具有多个光学子组件（1001）和印刷电路板（150）的光学收发器模块。收发器模块包括用于将光学子组件连接到印刷电路板的引线框架连接器（12,22）。引线框架连接器包括冲压 和弯曲的导电引线结构（30），所述导电引线结构（30）被包封在插入注塑塑料外壳（32）中。所述塑料外壳为所述引线框架中的导体提供电绝缘以及为所述成品部件提供机械支撑。所述引线框架连接器连接到 引线与光学子组件相关联并且表面安装到印刷电路板上以建立光学子组件和印刷电路板之间的连接。引线框架组件通常比使用柔性印刷电路板结构建立电连接 光学组件和收发器印刷 电路板

公开(公告)号：EP1711041A3

公开(公告)日：2008-05-21

申请号：EP06290551.8

申请日：2006-04-05

Applicant: FUJIKURA LTD.

Inventor： Ohara, Toshihiko, Fujikura Ltd., Sakura Works ,  Unami, Yoshiharu, Fujikura Ltd., Sakura Works ,  Inatani, Yuji, Fujikura Ltd., Sakura Works ,  Ito, Shoji, Fujikura Ltd., Sakura Works

IPC: H05K3/40

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/10234 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A method for manufacturing a wiring board comprising an insulating member, comprising: a penetrating hole formation process of forming a penetrating hole in the insulating member; a placement process of inserting a conductive connecting particle into the penetrating hole; a connecting particle pressing process of disposing the conductive layers on both surfaces of the insulating member, pressing the conductive layers toward the connecting particle in the penetrating hole, and deforming the connecting particle in the pressing direction to obtain the connecting member; and a patterning process of patterning the conductive layers, wherein, in the connecting particle pressing process, the pressing is performed such that the cross-sectional area in the direction along the insulating member surface of at least a portion of the connecting member is greater than the contact area of the connecting member with the conductive layers.

公开(公告)号：EP0722264B9

公开(公告)日：2008-02-27

申请号：EP96300028.6

申请日：1996-01-03

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Yamamoto, Osamu

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/20

CPC classification number: H01R9/2466 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/142 ,  H05K1/184 ,  H05K3/202 ,  H05K3/325 ,  H05K3/3447 ,  H05K3/4084 ,  H05K2201/0382 ,  H05K2201/0394 ,  H05K2201/09118 ,  H05K2201/0969

公开(公告)号：EP1887583A1

公开(公告)日：2008-02-13

申请号：EP06746598.9

申请日：2006-05-18

Applicant: Sumitomo Electric Industries, Ltd.

Inventor： OKA, Yoshio Osaka Works of Sumitomo Electric Industries, Ltd. ,  TAKII, Hitoshi Osaka Works of Sumitomo Electric Industries, Ltd. ,  HAYASHI, Noriki Osaka Works of Sumitomo Electric Industries, Ltd.

IPC: H01B1/22 ,  H01B1/00 ,  H05K3/12 ,  H05K3/46

CPC classification number: H01B1/22 ,  H05K1/095 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0245 ,  H05K2201/0394 ,  Y10T428/24322 ,  Y10T428/24339

Abstract: The present invention provides a conductive paste comprising flake conductive fillers having a 99% cumulative particle size of 25 µm or less and a binder resin as essential components. The flake conductive fillers are metal particles having a silver-copper alloy surface layer. The conductive paste according to the present invention is fused with a part of a copper foil circuit to which the conductive paste is to be connected during connection by heating and pressurization, and has high electrical conductivity and high fill ration in a via hole. Thus, the conductive paste according to the present invention provides a multilayer printed wiring board that has high reliability of connection and excellent interlayer connection.

Abstract translation: 本发明提供一种包含99％累积粒径为25μm以下的片状导电性填料和作为必需成分的粘合剂树脂的导电性糊剂。 片状导电填料是具有银 - 铜合金表面层的金属颗粒。 根据本发明的导电膏在通过加热和加压的连接期间与要连接的导电浆料的铜箔电路的一部分熔合，并且在通孔中具有高导电性和高填充量。 因此，根据本发明的导电膏提供了具有高连接可靠性和优异的层间连接的多层印刷线路板。

公开(公告)号：EP1744609A3

公开(公告)日：2007-06-27

申请号：EP06123074.4

申请日：2000-05-25

Applicant: IBIDEN CO., LTD.

Inventor： Asai, Motoo Ogaki-kita-kojou, Ibiden Co., Ltd. ,  Wang, Dongdong Ogaki-kita-kojou, Ibiden Co., Ltd. ,  Mori, Takahiro Ogaki-kita-kojou, Ibiden Co., Ltd.

IPC: H05K3/46

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: The present invention relates to a multi-layer printed circuit board comprising a core substrate (30) having through holes (36); and an interlayer resin insulating layer (40) built up on said core substrate, wherein said through holes are constituted by filling a first metal layer (24) formed by electroplating, a metal film formed by electroless plating, sputtering or evaporation and a second metal layer (32) formed by electroplating.

Abstract translation: 本发明涉及一种包括具有通孔（36）的核心基板（30）的多层印刷电路板; 和在所述核心基板上形成的层间树脂绝缘层（40），其中所述通孔由通过电镀形成的第一金属层（24），通过无电镀形成的金属膜，溅射或蒸发和第二金属 通过电镀形成的层（32）。

公开(公告)号：EP1283662A4

公开(公告)日：2007-01-10

申请号：EP02710365

申请日：2002-01-29

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： TAKASE YOSHIHISA ,  NAKAMURA TSUNESHI

IPC: H05K3/40 ,  H05K3/00 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/462 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/384 ,  H05K3/385 ,  H05K3/4069 ,  H05K3/423 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0733 ,  H05K2203/108 ,  H05K2203/1461 ,  Y10T29/49155

Abstract: A multi-layer printed circuit board comprising, placed one upon another, a plurality of laminating double-side circuit board and a plurality of interlayer connecting prepregs, wherein a via hole extending from a conductor circuit side on one surface of the laminating double-side circuit board up to the conductor circuit on the other surface is provided and is filled with a conductive substance to mutually connect conductor circuits on the opposite surfaces of the laminating double-side circuit board, a pad portion of a laminating double-side circuit board and a pad portion of another laminating double-side circuit board are stacked via an interlayer connecting prepreg so as to allow a conductive substance-filled through hole in the interlayer connecting prepreg to face the pad portions, thereby electrically connecting the pad portions on the surfaces of the laminating double-side circuit boards. Accordingly, multi-layer printed circuit board excellent in connecproduction time.

公开(公告)号：EP0826152B1

公开(公告)日：2006-11-15

申请号：EP96915407.9

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WOOD, Alan, G. ,  FARNWORTH, Warren, M. ,  AKRAM, Salman ,  HEMBREE, David, R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/316 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

公开(公告)号：EP1711041A2

公开(公告)日：2006-10-11

申请号：EP06290551.8

申请日：2006-04-05

Applicant: FUJIKURA LTD.

Inventor： Ohara, Toshihiko, Fujikura Ltd., Sakura Works ,  Unami, Yoshiharu, Fujikura Ltd., Sakura Works ,  Inatani, Yuji, Fujikura Ltd., Sakura Works ,  Ito, Shoji, Fujikura Ltd., Sakura Works

IPC: H05K3/40

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4046 ,  H05K3/4069 ,  H05K3/4602 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/10234 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A method for manufacturing a wiring board comprising an insulating member, comprising: a penetrating hole formation process of forming a penetrating hole in the insulating member; a placement process of inserting a conductive connecting particle into the penetrating hole; a connecting particle pressing process of disposing the conductive layers on both surfaces of the insulating member, pressing the conductive layers toward the connecting particle in the penetrating hole, and deforming the connecting particle in the pressing direction to obtain the connecting member; and a patterning process of patterning the conductive layers, wherein, in the connecting particle pressing process, the pressing is performed such that the cross-sectional area in the direction along the insulating member surface of at least a portion of the connecting member is greater than the contact area of the connecting member with the conductive layers.

Abstract translation: 一种用于制造包括绝缘构件的布线板的方法，包括：在所述绝缘构件中形成贯通孔的贯通孔形成工序; 将导电性连接粒子插入贯通孔的配置工序; 将导电层配置在绝缘部件的两面上的连接粒子压制工序，将导电层压向贯通孔内的连接粒子，使连接粒子沿加压方向变形，得到连接部件; 以及对导电层进行图案化的图案化工序，其中，在连接粒子压制工序中，进行加压，使得沿着连接部件的至少一部分的绝缘部件表面的方向的截面积大于 连接构件与导电层的接触面积。

公开(公告)号：EP1691206A2

公开(公告)日：2006-08-16

申请号：EP06075592.3

申请日：1996-04-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wood, Alan G. ,  Farnworth, Warren M. ,  Akram, Salman ,  Hembree, David R.

IPC: G01R31/02 ,  G01R1/073 ,  G01R31/316 ,  G01R1/04 ,  H01L21/66

CPC classification number: G01R1/07314 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/80 ,  H01L24/85 ,  H01L2224/16145 ,  H01L2224/48 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H01L2224/78 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Abstract translation: 一种用于测试未封装的半导体裸片的方法和设备包括母板（10）和安装在母板（10）上并且适于与裸片（14）建立暂时电连接的多个互连（12）。 互连件（12）可以形成有硅衬底（20）和凸起的接触构件（16），用于接触管芯（14）的接合焊盘（22）。 或者，可以用安装在绝缘膜（74）上的微凸块接触构件（16）形成互连（16）。 母板（10）允许为了速度和功能而单独测试每个管芯（14），并且还使用标准的老化炉并行地进行老化测试。 在替代实施例中，使用母板/子板布置来执行测试。 每个子板（82）包括互连（12），允许单独测试裸片（14）的速度和功能。 然后可以将多个子板（82）安装到母板（10）上，以使用标准的老化烘箱进行老化测试。

公开(公告)号：EP1659841A2

公开(公告)日：2006-05-24

申请号：EP06003039.2

申请日：1999-07-07

Applicant: IBIDEN CO., LTD.

Inventor： Tsukada, Kiyotaka ,  Takada, Masaru ,  Chihara, Kenji

IPC: H05K3/42 ,  H05K1/11

CPC classification number: H05K1/0265 ,  H01L21/486 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/027 ,  H05K3/421 ,  H05K3/4652 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/0353 ,  H05K2203/0554 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A printed circuit board and a method for manufacturing the same that facilitates the formation of an upper surface pattern and prevents a lower surface metal foil from being damaged when forming a blind via hole with a laser is provided. A lower surface and an upper surface of an insulative substrate (5) are respectively coated with a lower surface metal foil (220) and an upper surface metal foil (210), the thickness of which is less than that of the lower surface metal foil (220). Next, an opening (213) is formed in the upper surface metal foil at a location corresponding to a blind via hole formation portion (35) of the insulative substrate. A blind via hole (3), the bottom of which is the lower surface metal foil, is formed by emitting a laser (8) against the blind via hole formation portion (35) through the opening (213). Then, a metal plating film (23) is applied to the wall of the blind via hole (3), and an upper surface pattern (21) and a lower surface pattern (22) are formed through etching.

Abstract translation: 提供一种印刷电路板及其制造方法，其在形成具有激光的盲孔时有利于形成上表面图案并防止下表面金属箔被损坏。 绝缘基板（5）的下表面和上表面分别涂覆有下表面金属箔（220）和上表面金属箔（210），其厚度小于下表面金属箔的厚度 （220）。 接下来，在上表面金属箔的与绝缘基板的盲通孔形成部（35）对应的位置形成开口（213）。 通过开口（213）向盲通孔形成部分（35）发射激光（8），形成其底部为下表面金属箔的盲通孔（3）。 然后，将金属镀膜（23）施加到盲孔（3）的壁上，通过蚀刻形成上表面图案（21）和下表面图案（22）。