公开(公告)号：EP1659625A2

公开(公告)日：2006-05-24

申请号：EP05028348.0

申请日：1999-03-19

Applicant: SEIKO EPSON CORPORATION

Inventor： Hashimoto, Nobuaki Seiko Epson Corporation

IPC: H01L23/12 ,  H01L23/498

CPC classification number: H01L24/10 ,  H01L21/486 ,  H01L21/563 ,  H01L23/13 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05548 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/07811 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15183 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/386 ,  H05K3/4038 ,  H05K2201/0305 ,  H05K2201/0394 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05647 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A semiconductor device comprises a substrate (214) in which penetrating holes (214a) are formed, the substrate (214) having a first and a second side opposite to each other, said penetrating holes (214a) having first openings on said first side and second openings on said second side; a semiconductor chip (112) having electrodes; a conductive member (118) directly formed over a region including said penetrating holes (214a) on said first side of said substrate (214), and electrically connected to said electrodes of said semiconductor chip (112); and external electrodes (16) which are provided through said penetrating holes (214a), electrically connected to said conductive member (118), and extending as far as outside of said second side of said substrate (214), wherein said substrate (214) is formed of a material of a higher elasticity than said external electrodes (16); and wherein protrusions (220) are formed in the internal wall surfaces of said penetrating holes (214a) by said material constituting said substrate (214). The protrusions (220) form extremities of said first openings.

Abstract translation: 半导体器件包括其中形成有穿透孔（214a）的衬底（214），衬底（214）具有彼此相对的第一和第二侧，所述穿透孔（214a）在所述第一侧上具有第一开口并且 在所述第二侧上的第二开口; 具有电极的半导体芯片（112） 在所述衬底的所述第一侧上的包括所述穿透孔的区域上直接形成并与所述半导体芯片的所述电极电连接的导电部件; 和通过所述通孔提供的外部电极，所述外部电极与所述导电部件电连接并且延伸到所述基板的所述第二侧的外部， 由弹性比所述外部电极（16）高的材料形成; 并且其中突起（220）由构成所述衬底（214）的所述材料形成在所述穿透孔（214a）的内壁表面中。 突起（220）形成所述第一开口的末端。

公开(公告)号：EP0971570A4

公开(公告)日：2006-01-04

申请号：EP98901002

申请日：1998-01-23

Applicant: IBIDEN CO LTD

Inventor： TAKADA MASARU ,  TSUKADA KIYOTAKA ,  KOBAYASHI HIROYUKI ,  MINOURA HISASHI ,  UKAI YOSHIKAZU ,  KONDO MITSUHIRO

IPC: B23K26/00 ,  H01L21/48 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/34 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: When a printed wiring board which has inner layer conductor circuits (161 and 131) between insulating layers (101 - 103) and blind via-holes (141 and 142) made from the top surface of the insulating layer to the inner layer conductor circuits is manufactured, a hole (160) is provided beforehand in the center part of the inner layer conductor circuits (161) at the bottom of the blind via-hole (141), and a laser beam is applied from the top surface side of the insulating layer to form the blind via-holes (141 and 142). After that, metal plating films are formed on the surfaces of the inner layer conductor circuits (131 and 161) and the blind via-holes (141 and 142).

Abstract translation: 一种制造印刷电路板（210）的方法，包括由合成树脂制成的至少两个绝缘层（211,212,213），布置在绝缘层之间的内层导体电路（221-225）和多个盲孔（ 3A-3E），其由最外表面朝向内层导体电路（221-225）形成，并且通过在形成盲通孔（3A-3E）的每一部分上依次照射激光束而具有不同的深度，其特征在于，最浅盲 通过使用具有形成标准孔所需的能量强度的标准激光束（242）将通孔（3A-3E）形成为标准孔，并且将标准激光束（242）多次照射 形成具有更深深度的盲孔（3B，3D，3E）。

公开(公告)号：EP1173051A4

公开(公告)日：2005-02-02

申请号：EP00900913

申请日：2000-01-25

Applicant: SONY CHEMICALS CORP

Inventor： KURITA HIDEYUKI ,  TANIGUCHI MASATO

IPC: G02F1/1345 ,  H05K1/14 ,  H05K3/00 ,  H05K3/30 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K3/361 ,  H05K3/305 ,  H05K3/323 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0154 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09709 ,  H05K2201/10977 ,  H05K2203/0733 ,  H05K2203/0759

Abstract: A flexible printed wiring board (10) in which a metallic bump (1a) of a first flexible printed wiring part (1) is connected to a connection pad (2a) of a second flexible wiring part (2), wherein the first flexible printed wiring part (1) is composed of a conductive layer (4) and an insulating layer (5) adjacent to the conductive layer (4), a hole (A) reaching the conductive layer is made in the insulating layer (5), a metallic plug (6) is formed in the hole (A) by electroplating, and the end of the metallic plug (6) projecting from the insulating layer (5) serves as a metallic bump (1a). As many flexible printed wiring boards as possible are produced from a laminated sheet for a flexible printed wiring having a predetermined size.

公开(公告)号：EP1484952A1

公开(公告)日：2004-12-08

申请号：EP03703355.2

申请日：2003-02-21

Applicant: Fujikura Ltd.

Inventor： ITO, Shouji, FUJIKURA LTD. SAKURA WORKS ,  NAKAO, Osamu, FUJIKURA LTD. SAKURA WORKS ,  HIGUCHI, Reiji, FUJIKURA LTD. SAKURA WORKS ,  OKAMOTO, Masahiro, FUJIKURA LTD. SAKURA WORKS

IPC: H05K3/46 ,  H05K1/11 ,  H05K3/40

CPC classification number: H05K3/4617 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0394 ,  H05K2201/0969 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0191 ,  H05K2203/1453 ,  Y10T29/49165 ,  Y10T428/12181 ,  Y10T428/24917

Abstract: A multilayer wiring board assembly component comprises: an insulating substrate component (the insulating resin layer 111); a conductive layer 112 formed on one surface of said insulating substrate component 111 in the form of an electrode pattern; an adhesive layer 113 formed on the other surface of said insulating substrate component 111; and a conductive resin composition 115 with which is filled a through hole passing through said insulating substrate component 111, said adhesive layer and said conductive layer in order to make interlayer interconnection. The bore diameter of the conductive layer portion 114b of the through hole 114 is smaller than the bore diameter of the insulating resin layer portion and the adhesive layer portion 114a to establish electrical connection between the conductive resin composition 115 and the conductive layer 112 by the rare surface 112a of the conductive layer 112.

Abstract translation: 一种多层电路板的安装部件包括：绝缘基片部件（在绝缘树脂层111）; 一导电层112上形成的电极图案的形成所述绝缘基板组件111的一个表面上; 形成在所述绝缘基板组件111的另一表面上的粘合层113; 和导电性树脂组合物115与所有其填充穿过所述绝缘基板组件111的通孔，所述粘合层和所述，为了使层间互连导电层。 贯通孔114的导电层部114b的孔直径大于所述绝缘树脂层的部分的孔直径和粘结层部分114A以建立由所述罕见的导电性树脂组合物115和导电层112之间的电连接更小的 导电层112 的面112a

公开(公告)号：EP1432024A2

公开(公告)日：2004-06-23

申请号：EP03028922.7

申请日：2003-12-17

Applicant: FUJIKURA LTD.

Inventor： Yamamoto, Satoshi ,  Takizawa, Takashi

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/4061 ,  H05K2201/0394 ,  H05K2203/016 ,  H05K2203/128 ,  H01L2924/00

Abstract: A method of forming a penetration electrode in which an electroconductive substance is inserted into a micropore that has one end blocked off only by wiring and a pad formed by an electroconductive substance without the wiring and pad being broken. In this method of forming a penetration electrode, an electroconductive substance is inserted into the micropore that penetrates a substrate and that has one aperture blocked off by an electroconductive thin film. After a protective member that holds the electroconductive thin film is provided on a surface on the electroconductive thin film side of the substrate, an electroconductive substance is inserted from the other aperture of the micropore.

Abstract translation: 形成其中的贯通电极到导电物质的方法被插入到的微孔（13）做有一个端挡着仅通过布线，并通过在导电物质没有布线和焊盘形成的垫被打破。 在导电性物质形成的贯通电极的该方法（14）被插入到所述微孔没有穿透基板和已做一个孔挡着在导电薄膜（12）。 后的保护部件（20）保持所述导电性确实提供了一种表面上，以导电性物质的基板的导电薄膜侧薄膜由微孔的另一个孔插入。

公开(公告)号：EP1009204A4

公开(公告)日：2004-06-23

申请号：EP98923140

申请日：1998-06-05

Applicant: IBIDEN CO LTD

Inventor： ENOMOTO RYO ,  HIRAMATSU YASUJI

IPC: H05K3/00 ,  H05K3/28 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4617 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/382 ,  H05K3/386 ,  H05K3/423 ,  H05K3/4602 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/035 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0733 ,  H05K2203/1189 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Holes (40a) are formed with a laser beam through an insulating substrate (40) on which a metallic layer (42) is formed. After the holes (40a) are formed, via holes (36a) are formed by filling up the holes (40a) with a metal (46) and a conductor circuit (32a) is formed by etching the metallic layer (42). Then, a single-sided circuit board (30A) is formed by forming projecting conductors (38a) on the surfaces of the via holes (36a). The projecting conductors (38a) of the circuit board (30A) are put on the conductor circuit (32b) of another single-sided circuit board (30B) with adhesive layers (50) composed of an uncured resin in between and heated and pressed against the circuit (32b). The projecting conductors (38a) get in the uncured resin by pushing aside the resin and are electrically connected to the circuit (32b). Since single-sided circuit boards (30A, 30B, 30C, and 30D) can be inspected for defective parts before the boards (30A, 30B, 30C, and 30D) are laminated upon another, only defectless single-sided circuit boards can be used in the step of lamination.

公开(公告)号：EP1406477A1

公开(公告)日：2004-04-07

申请号：EP01974745.0

申请日：2001-10-09

Applicant: MEIKO ELECTRONICS CO., LTD.

Inventor： MITSUHASHI, Takayuki, c/o MEIKO ELECTRONICS CO LTD ,  KATAGIRI, Yasuyuki, c/o MEIKO ELECTRONICS CO. LTD. ,  MATSUDA, Takahiro, c/o MEIKO ELECTRONICS CO., LTD. ,  KANDA, Takeshi, c/o MEIKO ELECTRONICS CO., LTD.

IPC: H05K3/46

CPC classification number: H05K3/4602 ,  H05K3/0035 ,  H05K3/423 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/096 ,  H05K2203/0733

Abstract: A core substrate (B) for being used in producing a multilayer circuit board in a manner that a plurality of unit circuit boards are laid on the upper and lower surfaces of the core substrate comprises two insulation layers (10A, 10B) laid with a conductor land part (11A) between. The insulation layers have a pair of laser-machined holes (12A, 12B) above and below the conductor land part, each extending from the surface of the insulation layer up to the conductor land part. The pair of laser-machined holes are filled with an electroplating material to form a pair of columnar conductors (13A, 13B) electrically connected through the conductor land part. Since all layers can be interconnected through a series structure formed of an electro copper plating material, the core substrate is useful for producing a multilayer circuit board in which low resistance and fine patterning can be realized.

Abstract translation: 当通过在保持导体接地部分（11A）的同时铺设两个绝缘层（10A，10B）的上表面和下表面上放置多个单元电路板来制造多层电路板时使用的核心基板（B） 在它们之间，通过激光加工在导体接地部分的上方和下方通过激光加工制造一对孔（12A，12B），同时从绝缘层的表面延伸到导体接合部分并填充电镀材料，从而形成一对柱状 导体（13A，13B）通过导体接地部电连接。

公开(公告)号：EP1035580A3

公开(公告)日：2003-12-03

申请号：EP00301805.8

申请日：2000-03-06

Applicant: Altera Corporation

Inventor： Anderson, Sidney Larry ,  Long, Jon ,  Fritz, Donald S.

IPC: H01L23/498 ,  H01L21/58 ,  H01L23/31

CPC classification number: H01L24/32 ,  H01L21/4853 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/16237 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/112 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2203/041 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/0401 ,  H01L2924/00012

Abstract: An integrated circuit package is constructed to potential reduce stress and damage to an integrated circuit die. A rigid transition medium (42) is attached using adhesive layers (38,40) and interfaces between a tape carrier (20) and the integrated circuit die (18). The integrated circuit package prevents damage such as die cracks and also enhances the service life of the packaged integrated circuit part.

公开(公告)号：EP1363483A2

公开(公告)日：2003-11-19

申请号：EP03010758.5

申请日：2003-05-14

Applicant: rotra Leiterplatten Produktions- und Vetriebs-GmbH

Inventor： Opitz, Rudi Walter ,  Stuckmann, Walter Paul Fritz ,  Kopf, Reinhold

IPC: H05K3/06 ,  H05K1/02

CPC classification number: H05K1/0265 ,  H05K1/0393 ,  H05K3/06 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09736 ,  H05K2203/1476 ,  H05K2203/302

Abstract: Verfahren zur Herstellung eines Mehrlagen-Leiterplatten-Verbundkörpers umfassend die folgenden Schritte:

Bereitstellen eines Leiterplatten-Rohlings (1), welcher aufweist eine Trägerplatte (2) und mindestens eine zur Führung von Leistungsströmen hinsichtlich der Dicke geeignete, elektrisch leitende, mit der Trägerplatte (2) flächig verbundene Leitungsschicht (3) und
Reduktion der Dicke eines Teils der mindestens einen Leitungsschicht (3) zur Schaffung einer Signal-Leitungsschicht (8).

Abstract translation: 该方法包括提供包括衬底（2）的电路板空白（1）和适于承载电力电流的厚度的至少一个导电层（3）。 导电层（3）的一部分的厚度被减小以产生信号传导层。 导电层具有厚度DL，其中150微米大约620毫米，优选DL400毫米。 多层电路板模块包含独立权利要求。

公开(公告)号：EP1346410A1

公开(公告)日：2003-09-24

申请号：EP01998999.5

申请日：2001-11-23

Applicant: Koninklijke Philips Electronics N.V.

Inventor： GREEN, Peter, W.

IPC: H01L23/12 ,  H01L21/48 ,  H01L27/12 ,  H01L27/04 ,  H01L21/822 ,  H01L21/84

CPC classification number: H05K1/0278 ,  H01L23/5381 ,  H01L27/00 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/0306 ,  H05K3/0064 ,  H05K3/4092 ,  H05K2201/0191 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2203/302 ,  H01L2924/00

Abstract: An electronic device (38) for mounting on a curved or flexible support (42) and a method for fabrication of the same. The electronic device comprises a flexible substrate (18) and a layer (2) of rigid material over the substrate having electronic components on its upper surface. Weakened regions (6) of the rigid layer (2) define contiguous portions of the rigid layer, and flexible connectors (16) extend between components on different portions. The rigid layer (2) can be fractured along the weakened regions (6) to afford flexibility.