公开(公告)号：EP1142457A1

公开(公告)日：2001-10-10

申请号：EP99959169.6

申请日：1999-12-24

Applicant: PPC Electronic AG

Inventor： WIDMER, Thomas

IPC: H05K3/46 ,  H05K1/11

CPC classification number: H05K1/115 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/4652 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/0207 ,  H05K2203/0353 ,  H05K2203/108

Abstract: The invention relates to a method for producing a multilayer printed circuit board which is produced by bonding laminate layers (20, 30, 40, 50) which each consist of a conductor layer (24, 25, 31, 32) and an insulating layer (16, 17; 28, 29) to a laminate core (10). According to the invention the via holes (33, 34) between the conductor layers (24, 32 and 25, 31) are formed by laser drilling through the individual laminate layers (40, 50) and then plated through.

公开(公告)号：EP1139353A2

公开(公告)日：2001-10-04

申请号：EP01301805.6

申请日：2001-02-28

Applicant: VICTOR COMPANY OF JAPAN, LTD.

Inventor： Shindoh, Motoshi ,  Segawa, Keiji ,  Otsuki, Mitsuru

IPC: H01C7/18

CPC classification number: H05K1/167 ,  H01C17/12 ,  H05K1/0206 ,  H05K1/165 ,  H05K3/388 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: The invention provides a production method capable of forming a thin film resistance element having a thickness and a shape controlled in a high accuracy in a printed circuit board (core material). The production method of a thin film resistance element formed on a printed circuit board, has the steps of forming a thin film resistance layer having a predetermined thickness on the printed circuit board through an insulation layer by a dry process used in producing a semiconductor, forming an electrically conductive layer on the thin resistance layer, and etching the electrically conductive layer selectively so as to make, at least, a pair of electrically conductive pads, resulting in the thin film resistance element having a predetermined value of resistivity between the pair of electrically conductive pads. Thereby, it is possible to form the thin film resistance element having a thickness and a shape controlled in a high accuracy on the printed circuit board (core material).

Abstract translation: 本发明提供一种能够形成具有一定厚度和在印刷电路板（芯材）的高精确度控制的形状的薄膜电阻元件的制造方法。 形成在印刷电路板的薄膜电阻元件的制造方法，具有形成在制造半导体使用的干法具有通过向绝缘层上的印刷电路板的预定厚度的薄膜电阻层的工序，形成 薄电阻层上的导电层，并且选择性地蚀刻导电层，以使至少一对导电焊盘，在薄膜电阻元件所得到的具有一对电之间的电阻率的预定值 导电衬垫。 由此，可以形成具有厚度和在高精度地控制在印刷电路板（芯材）的形状的薄膜电阻元件。

公开(公告)号：EP1102355A2

公开(公告)日：2001-05-23

申请号：EP00124311.2

申请日：2000-11-16

Applicant: JAPAN AVIATION ELECTRONICS INDUSTRY, LIMITED

Inventor： Tai, Tomishige ,  Koguchi, Mitsuo

IPC: H01R12/22

CPC classification number: H05K3/20 ,  H01R12/52 ,  H05K3/4038 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2203/0108 ,  H05K2203/0338 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49176 ,  Y10T29/4921 ,  Y10T29/4922 ,  Y10T29/49222

Abstract: A metallic thin film 15 is formed on a mold 11 having protrusions 12 complementary in shape to a conductor pattern to be formed; a substrate 17 having a transfer layer 16 of adherent (or adhesive) material applied to one side surface thereof is provided; and the transfer layer 16 side of the substrate is brought into intimate contact with the metallic thin film 15 laid over the protrusions 12, followed by pulling the transfer layer apart from the mold so as to transfer the metallic thin film 15 covering the protrusions 12 onto the transfer layer 16 to thereby form the conductor pattern 18 on the transfer layer 16.

Abstract translation: 在模具11上形成金属薄膜15，该模具11具有与要形成的导体图案互补形状的突起12; 提供具有施加到其一个侧表面上的粘附（或粘合）材料的转印层16的基板17; 并使基板的转印层16侧与铺设在突起12上的金属薄膜15紧密接触，然后将转印层拉离模具，以便将覆盖突起12的金属薄膜15转印到 转印层16从而在转印层16上形成导体图案18。

公开(公告)号：EP1096842A2

公开(公告)日：2001-05-02

申请号：EP00309489.3

申请日：2000-10-27

Applicant: Ajinomoto Co., Inc.

Inventor： Nakamura, Shigeo, c/o Aminoscience Lab. ,  Yokota, Tadahiko, c/o Aminoscience Lab.

IPC: H05K3/46

CPC classification number: H05K3/4069 ,  H05K3/0035 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/381 ,  H05K3/426 ,  H05K3/4661 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/066 ,  H05K2203/068 ,  H05K2203/085 ,  H05K2203/1383 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Herein is disclosed a method of manufacturing a multilayered printed wiring board using an adhesive film comprising a support base film provided with a mold release layer and a thermosetting resin composition laminated on the surface of the mold release layer, said resin composition being provided with the same or smaller area as or than that of the support base film, provided with thermal fluidity and being solid at normal temperatures.
The method includes:

1) directly covering at least the pattern processed portion on one surface or both surfaces of a pattern processed circuit substrate with the resin composition layer of said adhesive film, and performing laminating by heating and pressurizing under a vacuum condition; and
2) thermally curing the resin composition with the support base film attached thereto. Subsequent process steps include uncovering the resin composition layer by stripping at least the support base film.

Abstract translation: 在为圆盘游离缺失使用粘合剂膜，其包括支撑基膜，设置有脱模层和层叠在该脱模层的表面上的热固性树脂组合物，所述树脂组合物被提供有相同的制造多层印刷电路板的方法 或更小的区域或比该支撑基座的电影，设置有热流动性和在常温下为固体。 该方法包括：1）直接覆盖至少所述图案处理在一个表面上或部分用粘合剂。所述电影的树脂组合物层的图案加工的电路基板的两面，并通过加热进行层压和在真空条件下加压; 和2）热固化与膜连接到其上支撑基体的树脂组合物。 随后的工艺步骤包括：通过至少剥离支撑基片露出树脂组合物层。

公开(公告)号：EP0993039A4

公开(公告)日：2001-02-28

申请号：EP98929711

申请日：1998-06-26

Applicant: HITACHI CHEMICAL CO LTD

Inventor： URASAKI NAOYUKI ,  SHIMADA YASUSHI ,  TSURU YOSHIYUKI ,  NAKASO AKISHI ,  WATANABE ITSUO

IPC: H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H05K1/11 ,  H05K1/18 ,  H05K3/28 ,  H05K3/32 ,  H01L23/12 ,  H01L21/60

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/15192 ,  H05K1/114 ,  H05K1/189 ,  H05K3/28 ,  H05K3/323 ,  H05K2201/09509 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A substrate (8) for mounting semiconductor chips on which a semiconductor chip (3) having bumps (4) is mounted with an adhesive. The substrate is improved in reliability for secured connection and availability for mass production by coating the semiconductor chip mounting area of the substrate (8) with an insulating film (6) having an opening so as to prevent the exposure of wiring conductors (2) on the surface of the substrate (8) near the boundary of the semiconductor chip mounting area.

公开(公告)号：EP1030365A1

公开(公告)日：2000-08-23

申请号：EP98944278.5

申请日：1998-09-28

Applicant: IBIDEN CO., LTD.

Inventor： ASAI, Motoo Ogaki-kita-kojou, Ibiden kabushiki ,  MORI, Yoji Ogaki-kita-kojou, Ibiden kabushiki

IPC: H01L23/12 ,  H01L23/32

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/114 ,  H05K1/116 ,  H05K3/3457 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599

Abstract: According to the package board of the present invention, each soldering pad formed on the top surface of the package board, on which an IC chip is to be mounted, is small (133 to 170µm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also small. On the other hand, each soldering pad formed on the bottom surface of the package board, on which a mother board, etc. are to be mounted, is large (600µm in diameter), so the metallic portion occupied by the soldering pads on the surface of the package board is also large. Consequently, a dummy pattern 58M is formed between conductor circuits 58U and 58U for forming signal lines on the IC chip side surface of the package board thereby to increase the metallic portion on the surface and adjust the rate of the metallic portion between the IC chip side and the mother board side of the package board, protecting the package board from warping in the manufacturing processes, as well as during operation.

Abstract translation: 根据本发明的封装板，形成在其上安装有IC芯片的封装板的上表面上的每个焊盘的直径小（133至170μm），所以金属部分占据 由包装板表面的焊盘也很小。 另一方面，形成在其上安装有母板等的封装基板的底面上的每个焊盘的直径大（直径为600μm），所以由焊盘占据的金属部分 在包装板的表面也很大。 因此，在导体电路58U和58U之间形成虚设图形58M，用于在封装板的IC芯片侧表面上形成信号线，从而增加表面上的金属部分，并调节IC芯片侧之间的金属部分的速率 和封装板的母板侧，保护封装板在制造过程中以及在运行期间不发生翘曲。

公开(公告)号：EP1019986A1

公开(公告)日：2000-07-19

申请号：EP98952161.2

申请日：1998-10-07

Applicant: Dimensional Circuits Corp.

Inventor： GREGOIRE, George, D.

IPC: H01R9/09

CPC classification number: H05K3/005 ,  H05K1/095 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0014 ,  H05K3/061 ,  H05K3/107 ,  H05K3/1241 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/465 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09863 ,  H05K2201/09981 ,  H05K2203/0108 ,  H05K2203/025 ,  H05K2203/041 ,  H05K2203/0746 ,  H05K2203/095 ,  H05K2203/1189 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49167

Abstract: A wiring board construction (10) includes at least one microvia (12) disposed in a base substrate (14) and includes a deep imprinted cup shaped in the top surface thereof (24). A conductor material is disposed within the recess (26), and has a portion disposed at the bottom thereof. A conductor disposed at a bottom surface of the substrate opposite to the conductor material bottom portion (31) helps to complete an electrically conductive path through the substrate.

公开(公告)号：EP1014772A2

公开(公告)日：2000-06-28

申请号：EP99310007.2

申请日：1999-12-13

Applicant: Hitachi, Ltd.

Inventor： Aoyagi, Paul ,  Suga, Takashi ,  Kasukabe, Susumu ,  Kanda, Naoya ,  Hayashi, Yoshihiko

IPC: H05K7/14

CPC classification number: H05K1/0243 ,  H05K3/3447 ,  H05K3/429 ,  H05K9/0039 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10189 ,  H05K2201/10356

Abstract: This invention provides a coaxial cable arranged in a coaxial propagation mode wherein signal wires and surrounding grounds are disposed coaxially, a multilayer printed circuit board arranged in a strip line propagation mode and having three or more layers, comprising signal through holes connected to signal interconnections formed in a signal layer, and a pair of ground through holes connected to ground interconnections of a pair of ground layers sandwiching the signal layer, and sandwiching the signal through holes 30 like a flat plane between them, and a relay connector comprising signal leads connecting the coaxial cable and the multilayer printed circuit board, and a pair of ground plates sandwiching the signal leads, connected in a strip line propagation mode which reduces noise currents and unwanted radiation.

Abstract translation: 本发明提供一种以同轴传播模式布置的同轴电缆，其中信号线和周围接地同轴设置，布置成带状传播模式并具有三层或更多层的多层印刷电路板，包括连接到形成的信号互连的信号通孔 在一个信号层中，一对接地通孔连接到夹着信号层的一对接地层的接地互连，并且夹住信号通过它们之间的平面的孔30，以及一个中继连接器，包括连接 同轴电缆和多层印刷电路板，以及夹着信号引线的一对接地板，以带状传播模式连接，其降低噪声电流和不期望的辐射。

公开(公告)号：EP1011139A1

公开(公告)日：2000-06-21

申请号：EP98905817.7

申请日：1998-03-09

Applicant: IBIDEN CO., LTD.

Inventor： TAKADA, Masaru, Ibiden Co., Ltd ,  MINOURA, Hisashi, Ibiden Co., Ltd ,  TSUKADA, Kiyotaka, Ibiden Co., Ltd ,  KOBAYASHI, Hiroyuki, Ibiden Co., Ltd ,  KONDO, Mitsuhiro, Ibiden Co., Ltd

IPC: H01L23/12 ,  H05K3/46

CPC classification number: H01L24/49 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/021 ,  H05K1/113 ,  H05K1/114 ,  H05K3/0035 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/385 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4652 ,  H05K3/4697 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/0315 ,  H05K2203/0554 ,  H05K2203/1581 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: In a printed wiring board, an odd number (n) of conductive layers (11-13) and insulating layers (21-23) are alternately laminated upon another. The first conductive layer (11) is constituted as a parts connecting layer and the n-th conductive layer (13) is constituted as an external connecting layer which is connected to external connecting terminals (7). The second to (n-1)-th conductive layers (12) are constituted as current transmitting layers for transmitting internal currents. The surface of the n-th conductive layer (13) is coated with the outermost n-th insulating layer (23) in a state where the external connecting terminals (7) are exposed on the surface. It is preferable to constitute the initial insulating layers of a glass-cloth reinforced prepreg and the external insulating layers of a resin.

Abstract translation: 在印刷电路板中，奇数（n）个导电层（11-13）和绝缘层（21-23）交替层叠在另一个上。 第一导电层（11）构成为部件连接层，第n导电层（13）构成为连接到外部连接端子（7）的外部连接层。 第（n-1）个第二导电层（12）构成用于传输内部电流的电流传输层。 第n导电层（13）的表面在外部连接端子（7）暴露在表面上的状态下被最外面的第n绝缘层（23）涂覆。 优选构成玻璃布预浸料坯的初始绝缘层和树脂的外部绝缘层。

公开(公告)号：EP0844809A3

公开(公告)日：1999-12-01

申请号：EP97116093.2

申请日：1997-09-16

Applicant: IBIDEN CO, LTD.

Inventor： Ono, Yoshitaka ,  Goto, Akihiko ,  Niki, Ayao ,  Asai, Motoo

IPC: H05K3/28 ,  H05K3/38 ,  H05K3/40 ,  G03F7/038

CPC classification number: H05K3/244 ,  G03F7/032 ,  G03F7/0388 ,  H05K1/112 ,  H05K3/184 ,  H05K3/28 ,  H05K3/287 ,  H05K3/3457 ,  H05K3/384 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2203/0307 ,  H05K2203/0392 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T428/24917

Abstract: A solder resist composition comprises an acrylate of novolac type epoxy resin and an imidazole curing agent and has a viscosity of 0.5-10 Ps·s adjusted with glycol ether type solvent. A printed circuit board is formed by using such a solder resist composition.

Abstract translation: 本发明涉及一种印刷电路板，其包括布线基板，该布线基板设置有形成在所述基板的表面上的导体电路（5）和阻焊层（14），其中，在所述基板的表面上形成有粗糙层（11） 导体电路（5）。