公开(公告)号：EP1497860A2

公开(公告)日：2005-01-19

申请号：EP03726148.4

申请日：2003-03-27

Applicant: INTEL CORPORATION

Inventor： VANDENTOP, Gilroy ,  CHIU, Chia-Pin ,  NAIR, Rajendran ,  LI, Yian-Liang

IPC: H01L23/367

CPC classification number: H01L23/4006 ,  H01L23/13 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4093 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2023/405 ,  H01L2023/4056 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/732 ,  H01L2224/73253 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1427 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19041 ,  H01L2924/19042 ,  H05K1/0204 ,  H05K1/182 ,  H05K2201/09054 ,  H05K2201/10378 ,  H05K2201/10409 ,  H05K2201/10477 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: The present invention describes a method and apparatus for mounting a microelectronic device parallel to a substrate with an interposer and two heat sinks, one on each side of the substrate.

公开(公告)号：EP1399879A1

公开(公告)日：2004-03-24

申请号：EP02747862.7

申请日：2002-05-24

Applicant: Alien Technology Corporation

Inventor： CREDELLE, Thomas, Lloyd ,  GENGEL, Glenn ,  STEWART, Roger Green ,  JOSEPH, William, Hill

IPC: G06K19/077

CPC classification number: H01L24/96 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07752 ,  G06K19/07779 ,  G06K19/07783 ,  H01L24/24 ,  H01L24/82 ,  H01L24/95 ,  H01L29/0657 ,  H01L2224/24137 ,  H01L2224/24227 ,  H01L2224/95085 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/10158 ,  H01L2924/12041 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15155 ,  H01L2924/15165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01Q1/2208 ,  H01Q7/00 ,  H05K1/141 ,  H05K1/183 ,  H05K3/222 ,  H05K3/321 ,  H05K2201/10477 ,  Y10T29/49002 ,  Y10T29/49016 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Methods and apparatuses for an elecronic assembly. The electronic assembly has a first object created and separated from a host substrate. The first object has a first electrical circuitry therein. A carrier substrate is coupled to the first object wherein the first object is being recessed below a surface of the carrier substrate. The carrier substrate further includes a first carrier connection pad and a second carrier connection pad that interconnect with the first object using metal connectors. A receiving substrate, which is substantially planar, including a second electrical circuitry, a first receiving connection pad, and a second receiving connection pad that interconnect with the second electrical circuity using the metal connectors. The carrier substrate is coupled to the receiving substrate using the connection pads mentioned.

公开(公告)号：EP1093082A3

公开(公告)日：2002-06-12

申请号：EP00307934.0

申请日：2000-09-13

Applicant: FUJITSU LIMITED

Inventor： Kaiya, Hiroshi, c/o Fujitsu Limited ,  Honda, Toshiyuki, c/o Fujitsu Limited

IPC: G06K19/077

CPC classification number: G06K19/07747 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/07769 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/182 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module of a combination card can be incorporated into a card body with solder being easily melted, and heat transmission to portions other than the antenna connection terminals is reduced. A card body (1) is provided with an antenna. The module (20) includes a substrate (7) which has a terminal surface on which at least one external connection terminal (4) is formed and a mounting surface opposite to the terminal surface. An IC chip (8) is mounted on the mounting surface. The module includes at least one antenna connection terminal (21a, 21b) located on the mounting surface. The antenna connection terminal (21a) is connected to the antenna, and at least a part (21b) of the antenna connection terminal (21a, 21b) is exposed on the terminal surface.

公开(公告)号：EP1192842A1

公开(公告)日：2002-04-03

申请号：EP00917564.7

申请日：2000-03-13

Applicant: Telefonaktiebolaget L M Ericsson (Publ)

Inventor： WESTBERG, David

IPC: H05K3/32 ,  H01L23/34

CPC classification number: H05K1/0209 ,  H01L23/36 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/141 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/10674 ,  H01L2224/0401

Abstract: The present invention relates to a method and to an arrangement for connecting a component, such as a chip (6), on a substrate (7) to a conductive surface of a carrier, such as an earth plane (10) on a printed circuit board (8) having a conductive layer (11) in a so-called compact design.

公开(公告)号：EP1158570A1

公开(公告)日：2001-11-28

申请号：EP01115235.2

申请日：1995-06-08

Applicant: CUBIC MEMORY

Inventor： Pedersen, David ,  Finley, Michael ,  Sautter, Kenneth

IPC: H01L21/00 ,  H01L25/065

CPC classification number: H01L24/81 ,  H01L23/3737 ,  H01L23/4824 ,  H01L23/5256 ,  H01L23/5328 ,  H01L23/5382 ,  H01L23/5385 ,  H01L24/10 ,  H01L24/13 ,  H01L24/75 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/2919 ,  H01L2224/29399 ,  H01L2224/32145 ,  H01L2224/75 ,  H01L2224/81801 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3025 ,  H01R4/04 ,  H01R29/00 ,  H05K3/305 ,  H05K3/321 ,  H05K7/023 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10674 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2224/29099

Abstract: A method and apparatus for vertically interconnecting stacks of silicon segments. Each segment includes a plurality of adjacent die on a semiconductor wafer. The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls on each of the segments. After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to all four sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. The stack of electrically interconnected segments is then mounted below the surface of a circuit board and electrically connected to circuits on the board by applying traces of electrically conductive epoxy between the bonding pads on the top segment of the stack and the circuit board.

Abstract translation: 一种用于垂直互连硅片堆叠的方法和装置。 每个部分在半导体晶片上包括多个相邻的裸片。 使用一个或多个金属互连层在片段上互连多个管芯，该金属互连件延伸到段的全部四个侧面，以提供用于外部电连接点的边缘焊盘。 在芯片互连后，使用斜切切割从晶片的背面切割每个片段，以在每个片段上提供四个向内倾斜的边缘壁。 在从晶片切割片段之后，将片段放置在彼此的顶部以形成叠片。 堆叠中的垂直相邻的段通过将导电环氧树脂施加到堆叠的所有四个侧面而电互连。 堆叠中的每个段的向内倾斜的边缘壁提供凹部，其允许导电环氧树脂在片段被堆叠之后接近每个片段上的边缘接合焊盘和侧向电路。 电互连段的堆叠然后安装在电路板的表面下方，并通过在堆叠的顶部段和电路板上的接合焊盘之间施加迹线的导电环氧树脂电连接到电路板上的电路。

公开(公告)号：EP0977298A3

公开(公告)日：2001-10-24

申请号：EP99114940.2

申请日：1999-07-30

Applicant: Kyocera Corporation

Inventor： Sawa, Yoshinobu, c/o Kyocera Corporation ,  Koriyama, Shinichi, c/o Kyocera Corporation ,  Kitazawa, Kenji, c/o Kyocera Corporation ,  Minamiue, Hidehiro, c/o Kyocera Corporation

IPC: H01P1/04

CPC classification number: H01L23/66 ,  H01L24/48 ,  H01L2223/6611 ,  H01L2223/6627 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1423 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/16195 ,  H01L2924/1903 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01P1/047 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/142 ,  H05K3/0061 ,  H05K2201/09781 ,  H05K2201/10477 ,  H05K2201/1053 ,  H05K2201/10727 ,  H05K2203/1572 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: There is described a high-frequency module comprising a high-frequency device-mounting package and an external circuit board characterized in that said high-frequency device-mounting package (A) includes a dielectric substrate (1) having a first grounding layer (4) contained therein, said dielectric substrate (1) mounting a high-frequency device (2) on one surface thereof and having, formed on one surface thereof, first high-frequency signal transmission lines (3) connected to said high-frequency device (2), and having, formed on the other surface thereof, second high-frequency signal transmission lines (7) coupled to said first high-frequency signal transmission lines (3), said external circuit board (B) is constituted by a dielectric board (20) having third high-frequency signal transmission lines (25) and a second grounding layer (26), said third high-frequency signal transmission lines (25) being formed on one surface of said dielectric board (20), and said second grounding layer (26) being formed on the other surface of said dielectric board (20) or inside thereof; and said high-frequency device-mounting package (A) and said external circuit board (B) are arranged side by side, and the second high-frequency signal transmission lines (7) of the high-frequency device-mounting package (A) are electrically connected to the third high-frequency signal transmission lines (25) of the external circuit board (B) through linear electrically conducting members (31). The patterns of the second high-frequency signal transmission lines on the side of the high-frequency device-mounting package can be easily aligned with the patterns of the third high-frequency signal transmission lines on the side of the external circuit board, effectively reducing the transmission loss at the junction portions of the lines.

Abstract translation: 描述了一种包括高频器件安装封装和外部电路板的高频模块，其特征在于所述高频器件安装封装（A）包括具有第一接地层（4）的电介质基片（1） ），所述介质基板（1）在其一个表面上安装高频器件（2），并且在其一个表面上形成有连接到所述高频器件的第一高频信号传输线（3） 2），并且在其另一个表面上形成有耦合到所述第一高频信号传输线（3）的第二高频信号传输线（7），所述外部电路板（B）由电介质板 （20）具有第三高频信号传输线（25）和第二接地层（26），所述第三高频信号传输线（25）形成在所述电介质板（20）的一个表面上，所述第二高频信号传输线 接地层（ 26）形成在所述电介质板（20）的另一个表面上或其内部; 并且所述高频装置安装封装（A）和所述外部电路板（B）并排布置，并且所述高频装置安装封装（A）的第二高频信号传输线（7） 通过线性导电构件（31）电连接到外部电路板（B）的第三高频信号传输线（25）。 高频器件安装封装侧的第二高频信号传输线的图案可以容易地与外部电路板侧的第三高频信号传输线的图形对准，有效地减少 在线路的接合部分的传输损耗。

公开(公告)号：EP0976104A2

公开(公告)日：2000-02-02

申请号：EP97914230.4

申请日：1997-03-12

Applicant: PAV Card GmbH

Inventor： WILM, Robert

IPC: G06K19/077

CPC classification number: G06K19/07728 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/0775 ,  G06K19/07779 ,  G06K19/07781 ,  G06K19/07783 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01077 ,  H05K1/0212 ,  H05K1/142 ,  H05K1/182 ,  H05K1/183 ,  H05K3/0044 ,  H05K3/28 ,  H05K3/305 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3494 ,  H05K3/368 ,  H05K2201/0394 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10719 ,  H05K2201/10727 ,  H05K2201/10818 ,  H05K2201/10977 ,  H05K2203/0228 ,  H05K2203/0285 ,  H05K2203/107 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/01005

Abstract: The invention concerns a smart card, a connection arrangement and a method of producing a smart card, a semiconductor chip located on a module being inserted into a recess (24) in a card carrier so as to be connected electrically and mechanically. According to a first feature of the invention, during the milling-out of the recess, a contact bump section is exposed (22, 23) such that a reliable connection is provided between the module and induction or antenna coil (11). According to a second and third feature, the required electrical contacts are produced by soldering and the required mechanical contacts are produced by heat-sealing or fusion adhesives. Furthermore, the adhesive is provided with conductive particles and is compressed when the connection is made, such that the necessary electrical contact is brought about. According to a fourth feature, a special reinforcement frame comprising insulating sections is provided. The reinforcement frame is used to increase mechanical stability and absorb torsion forces and stresses which can occur when the card is used. At the same time, the reinforcement frame permits easy contact with strip conductors inside the card, e.g. for elements which form an antenna for contactless data-transmission.

Abstract translation: 本发明涉及智能卡，连接装置和制造智能卡的方法，位于模块上的半导体芯片被插入到卡片载体中的凹部（24）中，以便电和机械连接。 根据本发明的第一特征，在铣削凹槽期间，暴露接触凸块部分（22,23），使得在模块和感应或天线线圈（11）之间提供可靠的连接。 根据第二和第三特征，通过焊接产生所需的电触点，并且通过热密封或熔融粘合剂产生所需的机械触点。 此外，粘合剂设置有导电颗粒，并且在形成连接时被压缩，使得产生必要的电接触。 根据第四特征，提供了包括绝缘部分的特殊加强框架。 增强框架用于增加机械稳定性，并吸收使用卡时可能发生的扭转力和应力。 同时，加强框架允许容易地与卡内的带状导体接触，例如， 用于形成用于非接触式数据传输的天线的电感元件。

公开(公告)号：EP0860100A1

公开(公告)日：1998-08-26

申请号：EP97926183.0

申请日：1997-07-01

Applicant: Koninklijke Philips Electronics N.V.

Inventor： DE SAMBER, Mark, André ,  VAN DE WALLE, Gerjan, Franciscus, Arthur

IPC: H05K1 ,  H01G4 ,  H01L23 ,  H05K3 ,  H05K7

CPC classification number: H05K3/3442 ,  H01G4/306 ,  H01L23/49805 ,  H01L2224/16 ,  H01L2224/32225 ,  H05K2201/10477 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49787 ,  Y10T29/49789

Abstract: The invention relates to an electric component (surface mountable component) which can be mounted on the surface of a printed circuit board, and to a method of manufacturing said component. Such a component comprises a thin, electroconductive layer or stack of layers which is provided with end contacts and arranged on a support of an electrically insulating material. In accordance with the invention, the dimension of the layer or stack of layers in at least one direction parallel to the surface of the support is smaller than the dimension of the support in said direction, while leaving portions of the surface of the support clear on at least two sides of the layer or stack of layers, and end contacts for the layer or stack of layers are situated on the surface portions of the support which are free of this layer or stack of layers, the thickness of said end contacts being larger than the thickness of the layer or stack of layers. The method in accordance with the invention enables small-size electric components to be manufactured in which the end contacts form a reliable electric connection with the electroconductive layer or stack of layers of the component.

公开(公告)号：EP0788159A3

公开(公告)日：1998-06-17

申请号：EP96307734

申请日：1996-10-25

Applicant: LSI LOGIC CORP

Inventor： LIANG DEXIN ,  SCHNEIDER MARK R

IPC: H01L21/48 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3436 ,  H05K2201/10477 ,  H05K2203/041 ,  H05K2203/0415 ,  H05K2203/159 ,  H05K2203/306 ,  Y02P70/613 ,  H01L2224/29099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012

Abstract: An integrated circuit (12) is mounted on and interconnected with a circuit board (14) by an array of electrically conductive columns (16). The assembly (10) is fabricated by initially interconnecting the integrated circuit and the circuit board with an array of reflowable electrically conductive solder balls that correspond to the columns respectively. The circuit board is held with the integrated circuit extending downwardly therefrom. Sufficient heat is applied to cause the solder balls to reflow. The integrated circuit is pulled downwardly away from the circuit board by gravity such that the balls are stretched to form the columns, and the assembly is allowed to cool such that the columns solidify. A fixture may be provided against which the integrated circuit abuts after it has moved away from the circuit board by a predetermined distance such that the columns have a precisely determined height.

公开(公告)号：EP0616489A1

公开(公告)日：1994-09-21

申请号：EP93117992.3

申请日：1993-11-05

Applicant: MITSUI MINING & SMELTING CO., LTD.

Inventor： Saida, Muneo ,  Hirasawa, Yutaka ,  Yoshimura, Katsuhiro

IPC: H05K3/38 ,  H05K3/02

CPC classification number: H05K3/384 ,  H01L2924/0002 ,  H05K2201/0355 ,  H05K2201/10477 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0392 ,  H05K2203/0723 ,  Y10S428/901 ,  Y10S428/935 ,  Y10T428/12472 ,  Y10T428/12569 ,  Y10T428/24917 ,  Y10T428/28 ,  Y10T428/2804 ,  H01L2924/00

Abstract: The present invention provides a copper-clad laminate characterized in that an electrolytic copper foil (1) on the glossy surface side (1a) of which a copper electrodeposit (2) is formed, is bonded at its glossy surface side (1a) to one side or each of both sides of a substrate (3), which has a fine-pitch wiring (circuit) pattern and exhibits a high etching factor. The present invention further provides a copper-clad laminate which can be suitably employed in the production of such a printed wiring board.

Abstract translation: 本发明提供一种覆铜层压板，其特征在于，在其光滑面侧（1a）上形成有形成有铜电沉积物（2）的光泽面侧（1a）上的电解铜箔（1） 侧面或基板（3）的两侧，其具有细间距布线（电路）图案并且表现出高蚀刻因子。 本发明还提供一种可以适用于制造这种印刷电路板的覆铜层压板。