公开(公告)号：US20090194801A1

公开(公告)日：2009-08-06

申请号：US12025207

申请日：2008-02-04

Applicant: Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

Inventor： Francis Gabriel Celii ,  Robert Kraft ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Theodore S. Moise

IPC: H01L27/00 ,  H01L21/00

CPC classification number: H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

Abstract: A method of manufacturing a semiconductor device. The method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive residue is generated on sidewalls of the ferroelectric capacitor as a by-product of the patterning. The method also comprises removing the conductive residue using a physical plasma etch clean-up process that includes maintaining a substrate temperature that is greater than about 60° C.

Abstract translation: 一种制造半导体器件的方法。 该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的铁电层，其中作为图案化的副产品，在铁电电容器的侧壁上产生导电残留物。 该方法还包括使用包括保持大于约60℃的衬底温度的物理等离子体蚀刻清理工艺去除导电残留物。

公开(公告)号：US06982448B2

公开(公告)日：2006-01-03

申请号：US10803445

申请日：2004-03-18

Applicant: K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： K. R. Udayakumar ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L27/11507 ,  H01L28/57

Abstract: Hydrogen barriers and fabrication methods are provided for protecting ferroelectric capacitors (CFE) from hydrogen diffusion in semiconductor devices (102), wherein nitrided aluminum oxide (N—AlOx) is formed over a ferroelectric capacitor (CFE), and one or more silicon nitride layers (112, 117) are formed over the nitrided aluminum oxide (N—AlOx). Hydrogen barriers are also provided in which an aluminum oxide (AlOx, N—AlOx) is formed over the ferroelectric capacitors (CFE), with two or more silicon nitride layers (112, 117) formed over the aluminum oxide (AlOx, N—AlOx), wherein the second silicon nitride layer (112) comprises a low silicon-hydrogen SiN material.

Abstract translation: 提供了氢屏障和制造方法，用于保护铁电电容器（CFE）在半导体器件（102）中的氢扩散，其中氮化的氧化铝（N-AlO x X）为 形成在铁电电容器（CFE）上，并且在氮化的氧化铝（N-AlO x N）上形成一个或多个氮化硅层（112,117）。 还提供了氢屏障，其中在铁电电容器（C FE）上形成氧化铝（AlO x N，N-AlO x x） ，其上形成有氧化铝（AlO x N，N-AlO x）上的两个或更多个氮化硅层（112,117），其中第二氮化硅层（112 ）包括低硅氢SiN材料。

公开(公告)号：US06521042B1

公开(公告)日：2003-02-18

申请号：US08667660

申请日：1996-06-21

Applicant: Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

Inventor： Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

IPC: C30B2516

CPC classification number: H01L29/882 ,  B82Y10/00 ,  B82Y15/00 ,  C30B23/002 ,  C30B29/40 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02631 ,  Y10T117/1004 ,  Y10T117/1008

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

Abstract translation: 基于过程模型，通过质谱仪（204）反馈信号生长层厚度控制（206）的分子束外延（202）。 实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。

公开(公告)号：US06211035B1

公开(公告)日：2001-04-03

申请号：US09392988

申请日：1999-09-09

Applicant: Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

Inventor： Theodore S. Moise ,  Guoqiang Xing ,  Mark Visokay ,  Justin F. Gaynor ,  Stephen R. Gilbert ,  Francis Celii ,  Scott R. Summerfelt ,  Luigi Colombo

IPC: H01L2120

CPC classification number: H01L27/11502 ,  H01L21/0332 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55

Abstract: A via etch to contact a capacitor with ferroelectric between electrodes together with dielectric on an insulating diffusion barrier includes two-step etch with F-based dielectric etch and Cl- and F-based barrier etch.

Abstract translation: 在电极之间与电介质之间的电介质与绝缘扩散阻挡层之间的电介质接触电容器的通孔蚀刻包括基于F的电介质蚀刻和基于Cl和F的势垒蚀刻的两步蚀刻。

公开(公告)号：US6100200A

公开(公告)日：2000-08-08

申请号：US218563

申请日：1998-12-21

Applicant: Peter C. Van Buskirk ,  Michael W. Russell ,  Daniel J. Vestyck ,  Scott R. Summerfelt ,  Theodore S. Moise

Inventor： Peter C. Van Buskirk ,  Michael W. Russell ,  Daniel J. Vestyck ,  Scott R. Summerfelt ,  Theodore S. Moise

IPC: C23C14/04 ,  C23C14/34 ,  H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L28/55 ,  C23C14/046 ,  C23C14/34 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/2855

Abstract: The present invention is a method related to the deposition of a metallization layer in a trench in a semiconductor substrate. The focus of the invention is to sequentially perform heated deposition and etch unit processes to provide a good conformal film of metal on the inner surfaces of a via or trench. The deposition and etch steps can also be performed simultaneously.

Abstract translation: 本发明是涉及在半导体衬底中的沟槽中沉积金属化层的方法。 本发明的重点是依次执行加热沉积和蚀刻单元工艺以在通孔或沟槽的内表面上提供良好的金属保形膜。 沉积和蚀刻步骤也可以同时进行。

公开(公告)号：US6008917A

公开(公告)日：1999-12-28

申请号：US960444

申请日：1997-10-29

Applicant: Theodore S. Moise ,  Gary A. Frazier

Inventor： Theodore S. Moise ,  Gary A. Frazier

IPC: H04B10/17 ,  H04B10/24 ,  H04B10/02

CPC classification number: B82Y10/00 ,  H04B10/291

Abstract: Apparatus for optical communications (10, 20, 30, 60 90) includes an optically switched resonant tunneling device (12, 22, 42, 62, 92) being exposed to an input light. The optically switched resonant tunneling device (12, 22, 42, 62, 92) generates a first and second voltage levels in response to the intensity level of the input light. A lasing device (16, 28, 46, 68, 74, 100) is coupled to the optically switched resonant tunneling device (12, 22, 42, 62, 92). The lasing device (16, 28, 46, 68, 74, 100) generates and modulates an output light in response to the first and second voltage levels.

Abstract translation: 用于光通信的设备（10,20,30,60 90）包括暴露于输入光的光学开关谐振隧穿装置（12,22,42,62,92）。 光开关谐振隧穿装置（12,22,42,62,92）响应于输入光的强度电平产生第一和第二电压电平。 激光装置（16,28,46,68,74,100）耦合到光开关谐振隧穿装置（12,22,42,62,92）。 激光装置（16,28,46,68,74,100）响应于第一和第二电压电平产生和调制输出光。

公开(公告)号：US5985025A

公开(公告)日：1999-11-16

申请号：US382324

申请日：1995-02-01

Applicant: Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

Inventor： Francis G. Celii ,  Alan J. Katz ,  Yung-Chung Kao ,  Theodore S. Moise

IPC: C30B23/08 ,  C30B23/02 ,  C30B29/68 ,  H01L21/203 ,  H01L21/338 ,  H01L29/812 ,  H01L29/88 ,  C30B25/16

CPC classification number: H01L29/882 ,  B82Y10/00 ,  B82Y15/00 ,  C30B23/002 ,  C30B29/40 ,  H01L21/02392 ,  H01L21/02463 ,  H01L21/02546 ,  H01L21/02631 ,  Y10T117/1004 ,  Y10T117/1008

Abstract: Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

公开(公告)号：US08093070B2

公开(公告)日：2012-01-10

申请号：US11706722

申请日：2007-02-15

Applicant: Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

Inventor： Francis Gabriel Celii ,  Kezhakkedath R. Udayakumar ,  Gregory B. Shinn ,  Theodore S. Moise ,  Scott R. Summerfelt

IPC: H01L21/00

CPC classification number: H01L28/75 ,  H01L27/11507 ,  H01L28/55

Abstract: A method is provided for fabricating a ferroelectric capacitor structure including a method for etching and cleaning patterned ferroelectric capacitor structures in a semiconductor device. The method comprises etching portions of an upper electrode, etching ferroelectric material, and etching a lower electrode to define a patterned ferroelectric capacitor structure, and etching a portion of a lower electrode diffusion barrier structure. The method further comprises ashing the patterned ferroelectric capacitor structure using a first ashing process, where the ash comprises an oxygen/nitrogen/water-containing ash, performing a wet clean process after the first ashing process, and ashing the patterned ferroelectric capacitor structure using a second ashing process.

Abstract translation: 提供一种用于制造铁电电容器结构的方法，其包括在半导体器件中蚀刻和清洁图案化的铁电电容器结构的方法。 该方法包括蚀刻上电极的部分，蚀刻铁电材料，并蚀刻下电极以限定图案化的铁电电容器结构，以及蚀刻下电极扩散阻挡结构的一部分。 所述方法还包括使用第一灰化过程灰化所述图案化的铁电电容器结构，其中所述灰分包括含氧/氮/水的灰分，在所述第一灰化处理之后执行湿式清洁处理，以及使用 第二次灰化过程。

公开(公告)号：US20070298521A1

公开(公告)日：2007-12-27

申请号：US11669759

申请日：2007-01-31

Applicant: Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

Inventor： Yaw S. Obeng ,  Kezhakkedath R. Udayakumar ,  Scott Robert Summerfelt ,  Sanjeev Aggarwal ,  Francis Gabriel Celii ,  Lindsey H. Hall ,  Robert Kraft ,  Theodore S. Moise

IPC: H01L21/00

CPC classification number: H01L21/02071 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02263 ,  H01L21/31683 ,  H01L28/55 ,  H01L28/65

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.

Abstract translation: 提出了制造半导体器件的方法。 一方面，该方法包括在半导体衬底上形成导电和铁电材料层。 图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。 该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。 转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。 转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

公开(公告)号：US06819601B2

公开(公告)日：2004-11-16

申请号：US10454862

申请日：2003-06-05

Applicant: Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

Inventor： Jarrod Eliason ,  Bill Kraus ,  Hugh McAdams ,  Scott Summerfelt ,  Theodore S. Moise

IPC: G11C700

CPC classification number: G11C11/22

Abstract: A ferroelectric memory device is disclosed and comprises a logic programmable capacitance reference circuit. The circuit is adapted to generate a reference voltage during a sense mode of operation, wherein the reference voltage comprises a value that is a function of one or more memory conditions. The memory device further comprises a bit line pair, wherein a first bit line of the bit line pair has a ferroelectric capacitor coupled thereto for sensing thereof, and a second bit line of the bit line pair is coupled to the reference voltage. A sense circuit is coupled to the bit line pair and is configured to detect a data state associated with the ferroelectric capacitor using a voltage associated with the first bit line and the reference voltage on the second bit line.