公开(公告)号：US08624359B2

公开(公告)日：2014-01-07

申请号：US13253845

申请日：2011-10-05

申请人： Chung-Ying Yang ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

发明人： Chung-Ying Yang ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

IPC分类号： H01L23/544

CPC分类号： H01L23/3142 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/76895 ,  H01L23/3114 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L23/564 ,  H01L23/585 ,  H01L24/05 ,  H01L24/13 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/02377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2224/05552

摘要： A wafer level chip scale package (WLCSP) includes a semiconductor device including an active surface having a contact pad, and side surfaces. A mold covers the side surfaces of the semiconductor device. A RDL structure includes a first PPI line electrically connected to the contact pad and extending on the active surface of the semiconductor device. A UBM layer is formed over and electrically connected to the first PPI line. A seal ring structure extends around the upper periphery of the semiconductor device on the mold. The seal ring structure includes a seal layer extending on the same level as at least one of the first PPI line and the UBM layer. A method of manufacturing a WLCSP includes forming a re-routing laminated structure by simultaneously forming an interconnection line and a seal layer on the molded semiconductor devices.

摘要翻译： 晶片级芯片级封装（WLCSP）包括具有接触焊盘的有源表面和侧表面的半导体器件。 模具覆盖半导体器件的侧表面。 RDL结构包括电连接到接触焊盘并在半导体器件的有源表面上延伸的第一PPI线。 UBM层形成在第一PPI线上并电连接到第一PPI线。 密封环结构围绕模具上的半导体器件的上周围延伸。 密封环结构包括在与第一PPI线和UBM层中的至少一个相同的高度上延伸的密封层。 制造WLCSP的方法包括通过在模制的半导体器件上同时形成互连线和密封层来形成再布线层压结构。

公开(公告)号：US08581400B2

公开(公告)日：2013-11-12

申请号：US13272540

申请日：2011-10-13

申请人： Shih-Wei Liang ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Mirng-Ji Lii

发明人： Shih-Wei Liang ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Mirng-Ji Lii

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L21/76841 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/525 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02235 ,  H01L2224/02255 ,  H01L2224/0226 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81411 ,  H01L2224/81413 ,  H01L2224/81416 ,  H01L2224/81439 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2924/00

摘要： A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.

摘要翻译： 半导体器件包括依次形成在半导体衬底上的钝化层，第一保护层，互连层和第二保护层。 互连层具有暴露部分，其上形成有阻挡层和焊料凸块。 钝化层，第一保护层，互连层和第二保护层中的至少一个包括形成在导电焊盘区域外的区域中的至少一个槽。

公开(公告)号：US08994181B2

公开(公告)日：2015-03-31

申请号：US13212536

申请日：2011-08-18

申请人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

发明人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Shih-Wei Liang

IPC分类号： H01L23/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00

CPC分类号： H01L23/291 ,  H01L23/3192 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48681 ,  H01L2224/48684 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48866 ,  H01L2224/48881 ,  H01L2224/48884 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

摘要： Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.

摘要翻译： 提供了形成接合焊盘结构的机理。 接合焊盘具有凹陷区域，该凹陷区域由接合焊盘下方的钝化层中的开口形成。 上钝化层至少覆盖接合焊盘的凹陷区域，以减少凹陷区域中图案化和/或蚀刻残留物的捕获。 结果，焊盘腐蚀的可能性降低。

公开(公告)号：US08871629B2

公开(公告)日：2014-10-28

申请号：US13291550

申请日：2011-11-08

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/14 ,  G06F2217/40 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/02311 ,  H01L2224/0239 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/1405 ,  H01L2224/14133 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/1203 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1207 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/37001 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01024 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/00 ,  H01L2224/05552

摘要： In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.

摘要翻译： 在提高半导体器件的球强度的方法中，接收要形成为半导体器件的电连接的多个连接球的球形图案。 该图案包括彼此交叉的多个列和行。 球排列在列和行的交点处。 在球形图案的区域中的球的布置被修改，使得该区域不包括孤立的球。

公开(公告)号：US08692378B2

公开(公告)日：2014-04-08

申请号：US13312538

申请日：2011-12-06

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L23/34

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。

公开(公告)号：US20130140706A1

公开(公告)日：2013-06-06

申请号：US13312538

申请日：2011-12-06

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Ying-Ju Chen ,  Shih-Wei Liang

IPC分类号： H01L23/485 ,  H01L21/768

CPC分类号： H01L24/11 ,  H01L23/3192 ,  H01L23/562 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/02375 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05572 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012

摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.

摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。

公开(公告)号：US09117831B2

公开(公告)日：2015-08-25

申请号：US13004261

申请日：2011-01-11

申请人： Ching-Jung Yang ,  Yu-Wen Liu ,  Michael Shou-Ming Tong ,  Hsien-Wei Chen ,  Chung-Ying Yang ,  Tsung-Yuan Yu

发明人： Ching-Jung Yang ,  Yu-Wen Liu ,  Michael Shou-Ming Tong ,  Hsien-Wei Chen ,  Chung-Ying Yang ,  Tsung-Yuan Yu

IPC分类号： H01L23/00 ,  H01L23/58

CPC分类号： H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W1, and the second portion has a width W2. The width W1 is less than the width W2.

摘要翻译： 半导体器件包括具有电路区域和密封环区域的衬底。 密封圈区域围绕电路区域。 密封环结构设置在密封环区域的上方。 密封环结构具有在第一部分上方的第一部分和第二部分。 第一部分具有宽度W1，第二部分具有宽度W2。 宽度W1小于宽度W2。

公开(公告)号：US08217499B2

公开(公告)日：2012-07-10

申请号：US12952485

申请日：2010-11-23

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

IPC分类号： H01L23/544

CPC分类号： H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

摘要翻译： 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

公开(公告)号：US20120126359A1

公开(公告)日：2012-05-24

申请号：US12952485

申请日：2010-11-23

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen ,  Chung-Ying Yang

IPC分类号： H01L29/06 ,  H01L21/76

CPC分类号： H01L21/31144 ,  H01L21/32139 ,  H01L23/585 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for reducing partially etched materials is described. The structure includes a layout of an intersection area between two trenches. First, a large intersection area having a trapezoidal corner may be replaced with an orthogonal intersection between two trenches. The layout reduces the intersection area as well as the possibility of having partially etched materials left at the intersection area. The structure also includes an alternative way to fill the intersection area with either an un-etched small trapezoidal area or multiple un-etched square areas, so that the opening area at the intersection point is reduced and the possibility of having partially etched materials is reduced too.

摘要翻译： 描述了用于减少部分蚀刻的材料的结构。 该结构包括两个沟槽之间的交叉区域的布局。 首先，具有梯形角的大交叉区域可以用两个沟槽之间的正交交替来代替。 布局减少了交叉区域以及在交叉区域留下部分蚀刻的材料的可能性。 该结构还包括用未蚀刻的小梯形区域或多个未蚀刻的正方形区域填充交叉区域的替代方法，使得交点处的开口面积减小，并且部分蚀刻材料的可能性降低 太。

公开(公告)号：US09129816B2

公开(公告)日：2015-09-08

申请号：US13422846

申请日：2012-03-16

申请人： Jie Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Ying-Ju Chen

发明人： Jie Chen ,  Hsien-Wei Chen ,  Tsung-Yuan Yu ,  Ying-Ju Chen

IPC分类号： H01L21/66 ,  H01L23/00 ,  H01L23/482

CPC分类号： H01L22/34 ,  H01L22/30 ,  H01L22/32 ,  H01L23/4824 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05555 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/0603 ,  H01L2224/06179 ,  H01L2224/06505 ,  H01L2224/11015 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14153 ,  H01L2224/14155 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/207 ,  H01L2924/014

摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.

摘要翻译： 提供了一种用于测试电气连接的系统和方法。 在一个实施例中，可以制造一个或多个浮动焊盘，以与下部焊接金属化结构电连接。 然后可以进行测试以通过浮动垫测量底部金属化结构的电特性，以测试缺陷。 或者，可以在下凸点金属化上形成导电连接，并且可以在导电连接和下凸点金属化一起进行测试。