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公开(公告)号：US09129816B2
公开(公告)日：2015-09-08
申请号：US13422846
申请日：2012-03-16
申请人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
发明人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
IPC分类号： H01L21/66 , H01L23/00 , H01L23/482
CPC分类号： H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014
摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
摘要翻译： 提供了一种用于测试电气连接的系统和方法。 在一个实施例中，可以制造一个或多个浮动焊盘，以与下部焊接金属化结构电连接。 然后可以进行测试以通过浮动垫测量底部金属化结构的电特性，以测试缺陷。 或者，可以在下凸点金属化上形成导电连接，并且可以在导电连接和下凸点金属化一起进行测试。
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公开(公告)号：US20130241683A1
公开(公告)日：2013-09-19
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译： 提供一种形成电感器件的电感器件和方法。 在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。 虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。
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公开(公告)号：US09000876B2
公开(公告)日：2015-04-07
申请号：US13419272
申请日：2012-03-13
申请人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
发明人： Hao-Yi Tsai , Hsien-Wei Chen , Hung-Yi Kuo , Jie Chen , Ying-Ju Chen , Tsung-Yuan Yu
IPC分类号： H01F5/00 , H01F27/28 , H01F27/36 , H01L31/107 , H01L23/522 , H01L23/552 , H01L23/00 , H01L49/02 , H01L23/58
CPC分类号： H01L23/5227 , H01L21/768 , H01L23/5225 , H01L23/552 , H01L23/585 , H01L24/03 , H01L24/11 , H01L28/10 , H01L2224/02351 , H01L2224/0401 , H01L2224/06515 , Y10T29/4902
摘要： An inductor device and method of forming the inductor device are provided. In some embodiments the inductor device includes a post passivation interconnect (PPI) layer disposed and an under bump metallization (UBM) layer, each disposed over a substrate. The PPI layer forms a coil and dummy pads. The dummy pads are disposed around a substantial portion of the coil to shield the coil from electromagnetic interference. A first portion of the UBM layer is electrically coupled to the coil and configured to interface with an electrical coupling member.
摘要翻译： 提供一种形成电感器件的电感器件和方法。 在一些实施例中，电感器件包括设置在衬底上的后钝化互连（PPI）层和凸块下金属化（UBM）层。 PPI层形成线圈和虚拟垫。 虚拟焊盘围绕线圈的大部分设置，以屏蔽线圈免受电磁干扰。 UBM层的第一部分电耦合到线圈并且被配置为与电耦合构件相接合。
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公开(公告)号：US20130240883A1
公开(公告)日：2013-09-19
申请号：US13422846
申请日：2012-03-16
申请人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
发明人： Jie Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Ying-Ju Chen
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L22/34 , H01L22/30 , H01L22/32 , H01L23/4824 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/05008 , H01L2224/05124 , H01L2224/05144 , H01L2224/05147 , H01L2224/05166 , H01L2224/05541 , H01L2224/05555 , H01L2224/05569 , H01L2224/05572 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0603 , H01L2224/06179 , H01L2224/06505 , H01L2224/11015 , H01L2224/13006 , H01L2224/13022 , H01L2224/13026 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/14153 , H01L2224/14155 , H01L2924/01029 , H01L2924/00014 , H01L2924/207 , H01L2924/014
摘要： A system and method for testing electrical connections is provided. In an embodiment one or more floating pads may be manufactured in electrical connection with an underbump metallization structure. A test may then be performed to measure the electrical characteristics of the underbump metallization structure through the floating pad in order to test for defects. Alternatively, a conductive connection may be formed on the underbump metallization and the test may be performed on the conductive connection and the underbump metallization together.
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公开(公告)号：US20130140706A1
公开(公告)日：2013-06-06
申请号：US13312538
申请日：2011-12-06
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L24/11 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02166 , H01L2224/02375 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05541 , H01L2224/05552 , H01L2224/05572 , H01L2224/0603 , H01L2224/06131 , H01L2924/00014 , H01L2924/206 , H01L2924/00012
摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.
摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。
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公开(公告)号：US09806042B2
公开(公告)日：2017-10-31
申请号：US13448217
申请日：2012-04-16
申请人： Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Yu-Feng Chen , Tsung-Ding Wang
发明人： Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Yu-Feng Chen , Tsung-Ding Wang
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/0401 , H01L2224/05008 , H01L2224/05541 , H01L2224/05548 , H01L2224/05552 , H01L2224/05567 , H01L2224/05569 , H01L2224/05572 , H01L2224/05644 , H01L2224/0603 , H01L2224/06131 , H01L2224/06133 , H01L2224/06179 , H01L2224/1134 , H01L2224/13005 , H01L2224/13022 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13166 , H01L2224/13181 , H01L2224/16145 , H01L2224/16238 , H01L2224/81191 , H01L2924/00014 , H01L2924/10253 , H01L2924/1306 , H01L2924/014 , H01L2924/00 , H01L2924/207 , H01L2924/206
摘要： A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.
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公开(公告)号：US08994181B2
公开(公告)日：2015-03-31
申请号：US13212536
申请日：2011-08-18
申请人： Ying-Ju Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Shih-Wei Liang
发明人： Ying-Ju Chen , Hsien-Wei Chen , Tsung-Yuan Yu , Shih-Wei Liang
IPC分类号： H01L23/48 , H01L23/29 , H01L23/31 , H01L23/522 , H01L23/00
CPC分类号： H01L23/291 , H01L23/3192 , H01L23/5226 , H01L24/05 , H01L2224/02166 , H01L2224/0345 , H01L2224/03452 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05008 , H01L2224/05096 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05567 , H01L2224/05572 , H01L2224/05573 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/05684 , H01L2224/131 , H01L2224/13147 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48647 , H01L2224/48666 , H01L2224/48681 , H01L2224/48684 , H01L2224/48824 , H01L2224/48847 , H01L2224/48866 , H01L2224/48881 , H01L2224/48884 , H01L2924/00014 , H01L2924/00012 , H01L2924/014 , H01L2924/00
摘要： Mechanisms of forming a bond pad structure are provided. The bond pad has a recess region, which is formed by an opening in the passivation layer underneath the bond pad. An upper passivation layer covers at least the recess region of the bond pad to reduce trapping of patterning and/or etching residues in the recess region. As a result, the likelihood of bond pad corrosion is reduced.
摘要翻译： 提供了形成接合焊盘结构的机理。 接合焊盘具有凹陷区域，该凹陷区域由接合焊盘下方的钝化层中的开口形成。 上钝化层至少覆盖接合焊盘的凹陷区域，以减少凹陷区域中图案化和/或蚀刻残留物的捕获。 结果，焊盘腐蚀的可能性降低。
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公开(公告)号：US08871629B2
公开(公告)日：2014-10-28
申请号：US13291550
申请日：2011-11-08
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
CPC分类号： H01L24/14 , G06F2217/40 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/02311 , H01L2224/0239 , H01L2224/024 , H01L2224/0345 , H01L2224/0401 , H01L2224/05569 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/05681 , H01L2224/131 , H01L2224/13111 , H01L2224/1405 , H01L2224/14133 , H01L2224/14517 , H01L2224/16145 , H01L2224/16225 , H01L2224/17517 , H01L2224/81815 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/1203 , H01L2924/1205 , H01L2924/1206 , H01L2924/1207 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3511 , H01L2924/3512 , H01L2924/37001 , H01L2924/01047 , H01L2924/0105 , H01L2924/01024 , H01L2924/01079 , H01L2924/01028 , H01L2924/00 , H01L2224/05552
摘要： In a method of improving ball strength of a semiconductor device, a ball pattern of a plurality of connection balls to be formed as electrical connections for the semiconductor device is received. The pattern includes a number of columns and rows crossing each other. The balls are arranged at intersections of the columns and rows. An arrangement of balls in a region of the ball pattern is modified so that the region includes no isolated balls.
摘要翻译： 在提高半导体器件的球强度的方法中，接收要形成为半导体器件的电连接的多个连接球的球形图案。 该图案包括彼此交叉的多个列和行。 球排列在列和行的交点处。 在球形图案的区域中的球的布置被修改，使得该区域不包括孤立的球。
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公开(公告)号：US08692378B2
公开(公告)日：2014-04-08
申请号：US13312538
申请日：2011-12-06
申请人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
发明人： Tsung-Yuan Yu , Hsien-Wei Chen , Ying-Ju Chen , Shih-Wei Liang
IPC分类号： H01L23/34
CPC分类号： H01L24/11 , H01L23/3192 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L2224/02166 , H01L2224/02375 , H01L2224/0401 , H01L2224/05005 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05541 , H01L2224/05552 , H01L2224/05572 , H01L2224/0603 , H01L2224/06131 , H01L2924/00014 , H01L2924/206 , H01L2924/00012
摘要： A wafer level chip scale semiconductor device comprises a semiconductor die, a first under bump metal structure and a second under bump metal structure. The first under bump metal structure having a first enclosure is formed on a corner region or an edge region of the semiconductor die. A second under bump metal structure having a second enclosure is formed on an inner region of the semiconductor die. The first enclosure is greater than the second enclosure.
摘要翻译： 晶片级芯片级半导体器件包括半导体管芯，第一下凸块金属结构和第二凸块下金属结构。 具有第一外壳的第一下凸块金属结构形成在半导体管芯的拐角区域或边缘区域上。 具有第二外壳的第二下凸块金属结构形成在半导体管芯的内部区域上。 第一个外壳大于第二个外壳。
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公开(公告)号：US08581400B2
公开(公告)日：2013-11-12
申请号：US13272540
申请日：2011-10-13
申请人： Shih-Wei Liang , Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Mirng-Ji Lii
发明人： Shih-Wei Liang , Hsien-Wei Chen , Ying-Ju Chen , Tsung-Yuan Yu , Mirng-Ji Lii
CPC分类号： H01L24/11 , H01L21/76841 , H01L23/3114 , H01L23/3171 , H01L23/3192 , H01L23/525 , H01L24/05 , H01L24/13 , H01L24/16 , H01L2224/02235 , H01L2224/02255 , H01L2224/0226 , H01L2224/0345 , H01L2224/03452 , H01L2224/0346 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05124 , H01L2224/05147 , H01L2224/05571 , H01L2224/05609 , H01L2224/05611 , H01L2224/05639 , H01L2224/05644 , H01L2224/05655 , H01L2224/05664 , H01L2224/11334 , H01L2224/11849 , H01L2224/13006 , H01L2224/13022 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/16227 , H01L2224/81191 , H01L2224/81411 , H01L2224/81413 , H01L2224/81416 , H01L2224/81439 , H01L2224/81447 , H01L2224/81455 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/15788 , H01L2924/014 , H01L2924/00012 , H01L2924/01082 , H01L2924/01046 , H01L2924/01079 , H01L2924/01047 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor device includes a passivation layer, a first protective layer, an interconnect layer, and a second protective layer successively formed on a semiconductor substrate. The interconnect layer has an exposed portion, on which a barrier layer and a solder bump are formed. At least one of the passivation layer, the first protective layer, the interconnect layer and the second protective layer includes at least one slot formed in a region outside a conductive pad region.
摘要翻译： 半导体器件包括依次形成在半导体衬底上的钝化层，第一保护层，互连层和第二保护层。 互连层具有暴露部分，其上形成有阻挡层和焊料凸块。 钝化层，第一保护层，互连层和第二保护层中的至少一个包括形成在导电焊盘区域外的区域中的至少一个槽。
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