公开(公告)号：US11367683B2

公开(公告)日：2022-06-21

申请号：US16453222

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

公开(公告)号：US20210066495A1

公开(公告)日：2021-03-04

申请号：US17004187

申请日：2020-08-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Philipp Sebastian Koch ,  Stephan Pindl ,  Hans-Joachim Schulze

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/423

Abstract: A power semiconductor device includes a semiconductor body having a front side surface, and a first passivation layer arranged above the front side surface. The first passivation layer is a polycrystalline diamond layer.

公开(公告)号：US10573533B2

公开(公告)日：2020-02-25

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L23/31 ,  H01L21/268 ,  H01L21/04 ,  H01L21/225 ,  H01L21/285

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US10483133B2

公开(公告)日：2019-11-19

申请号：US15944306

申请日：2018-04-03

Applicant: Infineon Technologies AG

Inventor： Daniel Porwol ,  Edward Fuergut

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/28 ,  H01L23/00 ,  H01L23/31

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a plurality of semiconductor chips, wherein each semiconductor chip comprises a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on a carrier with the second main faces facing the carrier and applying an encapsulation material by transfer molding thereby forming the semiconductor chip panel, wherein the encapsulation material is applied so that the side faces of the semiconductor chips are covered with the encapsulation material while the first main faces are not.

公开(公告)号：US10361138B2

公开(公告)日：2019-07-23

申请号：US15607735

申请日：2017-05-30

Applicant: Infineon Technologies AG

Inventor： Michael Ledutke ,  Edward Fuergut

IPC: H01L23/31 ,  H01L21/66 ,  H01L21/56 ,  H01L21/673

Abstract: In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.

公开(公告)号：US20190013210A1

公开(公告)日：2019-01-10

申请号：US16116210

申请日：2018-08-29

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Irmgard Escher-Poeppel ,  Stephanie Fassl ,  Paul Ganitzer ,  Gerhard Poeppel ,  Werner Schustereder ,  Harald Wiedenhofer

IPC: H01L21/324 ,  H01L21/285 ,  H01L21/225 ,  H01L21/04 ,  H01L21/321 ,  H01L21/268 ,  H01L23/31

CPC classification number: H01L21/324 ,  H01L21/0455 ,  H01L21/0485 ,  H01L21/2254 ,  H01L21/2258 ,  H01L21/268 ,  H01L21/28512 ,  H01L21/28575 ,  H01L23/3157

Abstract: Various embodiments provide a method of reducing a sheet resistance in an electronic device encapsulated at least partially in an encapsulation material, wherein the method comprises: providing an electronic device comprising a multilayer structure and being at least partially encapsulated by an encapsulation material; and locally introducing energy into the multilayer structure for reducing a sheet resistance.

公开(公告)号：US09593009B2

公开(公告)日：2017-03-14

申请号：US14515304

申请日：2014-10-15

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Horst Theuss ,  Rainer Leuschner

IPC: B81B7/00 ,  H04R19/00 ,  H04R31/00 ,  B81C1/00 ,  B81B3/00 ,  H01L23/00

CPC classification number: B81B7/0041 ,  B81B3/0021 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81C1/00253 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/181 ,  H04R19/005 ,  H04R31/006 ,  H04R2201/003 ,  H01L2924/00

Abstract: A system and a method for forming a packaged MEMS device are disclosed. In one embodiment a packaged MEMS device includes a MEMS device having a first main surface with a first area along a first direction and a second direction, a membrane disposed on the first main surface of the MEMS device and a backplate adjacent to the membrane. The packaged MEMS device further includes an encapsulation material that encapsulates the MEMS device and that defines a back volume, the back volume having a second area along the first direction and the second direction, wherein the first area is smaller than the second area.

Abstract translation: 公开了一种用于形成封装的MEMS器件的系统和方法。 在一个实施例中，封装的MEMS器件包括具有第一主表面的MEMS器件，第一主表面具有沿着第一方向的第一区域和第二方向，设置在MEMS器件的第一主表面上的膜和邻近膜的背板。 封装的MEMS器件还包括封装MEMS器件并且限定后部体积的封装材料，后部体积具有沿第一方向和第二方向的第二区域，其中第一区域小于第二区域。

公开(公告)号：US20160365296A1

公开(公告)日：2016-12-15

申请号：US15176952

申请日：2016-06-08

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Edward Fuergut ,  Christian Kasztelan ,  Hsieh Ting Kuek ,  Teck Sim Lee ,  Sanjay Kumar Murugan ,  Lee Shuang Wang

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/495 ,  H01L23/29

CPC classification number: H01L23/3114 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/293 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/13064 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A device includes an encapsulation material and a first lead and a second lead protruding out of a surface of the encapsulation material. A recess extends into the surface of the encapsulation material. An elevation is arranged on the surface of the encapsulation material. The first lead protrudes out of the elevation.

Abstract translation: 一种装置包括封装材料和从包封材料的表面突出的第一引线和第二引线。 凹部延伸到封装材料的表面。 在封装材料的表面上布置有高度。 第一个引线突出了海拔高度。

公开(公告)号：US09412626B2

公开(公告)日：2016-08-09

申请号：US14935510

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L21/00 ,  H01L21/56 ,  H01L23/34 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/552

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。

公开(公告)号：US20160211226A1

公开(公告)日：2016-07-21

申请号：US14987820

申请日：2016-01-05

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Joachim Mahler ,  Ivan Nikitin

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/48 ,  H01L21/56 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4832 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments, an integrated circuit is provided. The integrated circuit may include a semiconductor chip and an electrically conductive composite material fixed to the semiconductor chip, wherein the electrically conductive composite material may include a metal, and wherein a coefficient of thermal expansion (CTE) value of the electrically conductive composite material may be lower than the CTE value of the metal.

Abstract translation: 在各种实施例中，提供集成电路。 集成电路可以包括固定到半导体芯片的半导体芯片和导电复合材料，其中导电复合材料可以包括金属，并且其中导电复合材料的热膨胀系数（CTE）值可以是 低于金属的CTE值。