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1.发明授权Structure and method for forming pillar bump structure having sidewall protection 有权用于形成具有侧壁保护的支柱凸块结构的结构和方法公开(公告)号：US07919406B2
公开(公告)日：2011-04-05
申请号：US12791127
申请日：2010-06-01
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/11462 , H01L2224/11472 , H01L2224/1182 , H01L2224/11849 , H01L2224/11906 , H01L2224/13082 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13562 , H01L2224/136 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/00014 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599
摘要： A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.
摘要翻译： 提供一种用于形成金属柱凸块结构的方法。 在一个实施例中，在半导体衬底上形成钝化层，并且在钝化层上方形成导电层。 在导电层之上设置图案化和蚀刻的光致抗蚀剂层，光致抗蚀剂层在其中限定至少一个开口。 金属层沉积在至少一个开口中。 光致抗蚀剂层的一部分沿着光致抗蚀剂层和金属层之间的一个或多个界面被蚀刻以形成空腔。 焊料材料沉积在至少一个开口中，焊料材料填充空腔和金属层上方的开口的一部分。 去除残留的光致抗蚀剂层和未形成在铜层之下的导电层。 然后将焊料材料重新包覆以封装金属层。
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公开(公告)号：US20130093079A1
公开(公告)日：2013-04-18
申请号：US13276090
申请日：2011-10-18
IPC分类号： H01L23/498
CPC分类号： H01L24/16 , H01L23/3114 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/81 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/061 , H01L2224/06132 , H01L2224/13014 , H01L2224/13022 , H01L2224/13027 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13541 , H01L2224/1405 , H01L2224/141 , H01L2224/16105 , H01L2224/16237 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01047 , H01L2924/206 , H01L2224/05552
摘要： A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
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公开(公告)号：US08193639B2
公开(公告)日：2012-06-05
申请号：US12750468
申请日：2010-03-30
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L23/485
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。
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公开(公告)号：US20110241202A1
公开(公告)日：2011-10-06
申请号：US12750468
申请日：2010-03-30
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L23/485
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.
摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上方并接触金属焊盘。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。
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公开(公告)号：US08729699B2
公开(公告)日：2014-05-20
申请号：US13276090
申请日：2011-10-18
IPC分类号： H01L23/48
CPC分类号： H01L24/16 , H01L23/3114 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L24/81 , H01L2224/0401 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05166 , H01L2224/05572 , H01L2224/05647 , H01L2224/061 , H01L2224/06132 , H01L2224/13014 , H01L2224/13022 , H01L2224/13027 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13541 , H01L2224/1405 , H01L2224/141 , H01L2224/16105 , H01L2224/16237 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/00012 , H01L2924/01047 , H01L2924/206 , H01L2224/05552
摘要： A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.
摘要翻译： 芯片包括衬底，衬底上的金属焊盘以及覆盖金属焊盘的边缘部分的钝化层。 在金属垫上形成金属支柱。 金属柱的一部分与金属垫的一部分重叠。 金属支柱的中心与金属垫的中心不对齐。
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公开(公告)号：US08753971B2
公开(公告)日：2014-06-17
申请号：US13427430
申请日：2012-03-22
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L21/44
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.
摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。
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公开(公告)号：US20120178252A1
公开(公告)日：2012-07-12
申请号：US13427430
申请日：2012-03-22
申请人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
发明人： Tzuan-Horng Liu , Shang-Yun Hou , Shin-Puu Jeng , Wei-Cheng Wu , Hsiu-Ping Wei , Chih-Hua Chen , Chen-Cheng Kuo , Chen-Shien Chen , Ming Hung Tseng
IPC分类号： H01L21/768
CPC分类号： H01L23/585 , H01L23/552 , H01L23/562 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05012 , H01L2224/05572 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/1147 , H01L2224/11912 , H01L2224/13022 , H01L2224/13147 , H01L2224/13655 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2224/05552 , H01L2924/00
摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.
摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。
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公开(公告)号：US20110227216A1
公开(公告)日：2011-09-22
申请号：US12725322
申请日：2010-03-16
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L24/11 , H01L24/05 , H01L24/13 , H01L2224/03912 , H01L2224/0401 , H01L2224/04042 , H01L2224/05022 , H01L2224/05083 , H01L2224/05184 , H01L2224/05541 , H01L2224/05572 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/11462 , H01L2224/1147 , H01L2224/11849 , H01L2224/13022 , H01L2224/1308 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13169 , H01L2224/45144 , H01L2224/48624 , H01L2224/48639 , H01L2224/48647 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/15788 , H01L2924/181 , H01L2924/19041 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2224/05005
摘要： An under-bump metallization (UBM) structure for a semiconductor device is provided. A passivation layer is formed over a contact pad such that at least a portion of the contact pad is exposed. A protective layer, such as a polyimide layer, may be formed over the passivation layer. The UBM structure, such as a conductive pillar, is formed over the underlying contact pad such that the underlying contact pad extends laterally past the UBM structure by a distance large enough to prevent or reduce cracking of the passivation layer and or protective layer.
摘要翻译： 提供了一种用于半导体器件的凸块下金属化（UBM）结构。 钝化层形成在接触焊盘上，使得接触焊盘的至少一部分被暴露。 可以在钝化层上方形成保护层，例如聚酰亚胺层。 诸如导电柱的UBM结构形成在下面的接触焊盘之上，使得下面的接触焊盘横向延伸越过UBM结构一个足够大的距离，以防止或减少钝化层和/或保护层的破裂。
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公开(公告)号：US20140070403A1
公开(公告)日：2014-03-13
申请号：US13612588
申请日：2012-09-12
申请人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
发明人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
IPC分类号： H01L21/56 , H01L23/498
CPC分类号： H01L23/3121 , H01L21/4846 , H01L21/56 , H01L21/6835 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/12105 , H01L2224/131 , H01L2224/19 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.
摘要翻译： 公开了包装方法和包装装置。 在一个实施例中，一种封装半导体器件的方法包括在载体上形成第一再分布层（RDL），以及在第一RDL上形成多个通过组装通孔（TAV）。 集成电路管芯耦合在第一RDL上，并且模制化合物形成在第一RDL，TAV和集成电路管芯上。 在模制化合物，TAV和集成电路模具上形成第二RDL。
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公开(公告)号：US09059107B2
公开(公告)日：2015-06-16
申请号：US13612588
申请日：2012-09-12
申请人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
发明人： Kuo Lung Pan , Ming Hung Tseng , Chen-Shien Chen
IPC分类号： H01L23/498 , H01L21/56 , H01L23/31 , H01L21/48 , H01L23/00 , H01L21/683 , H01L25/10 , H01L25/00 , H01L23/538
CPC分类号： H01L23/3121 , H01L21/4846 , H01L21/56 , H01L21/6835 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L25/105 , H01L25/50 , H01L2224/12105 , H01L2224/131 , H01L2224/19 , H01L2224/2919 , H01L2224/32225 , H01L2224/73253 , H01L2224/73267 , H01L2224/83005 , H01L2224/92244 , H01L2225/1035 , H01L2225/1041 , H01L2225/1058 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： Packaging methods and packaged devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes forming a first redistribution layer (RDL) over a carrier, and forming a plurality of through assembly vias (TAVs) over the first RDL. An integrated circuit die is coupled over the first RDL, and a molding compound is formed over the first RDL, the TAVs, and the integrated circuit die. A second RDL is formed over the molding compound, the TAVs, and the integrated circuit die.
摘要翻译： 公开了包装方法和包装装置。 在一个实施例中，一种封装半导体器件的方法包括在载体上形成第一再分布层（RDL），以及在第一RDL上形成多个通过组装通孔（TAV）。 集成电路管芯耦合在第一RDL上，并且模制化合物形成在第一RDL，TAV和集成电路管芯上。 在模制化合物，TAV和集成电路模具上形成第二RDL。
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