公开(公告)号：US20130026623A1

公开(公告)日：2013-01-31

申请号：US13194606

申请日：2011-07-29

申请人： Yu-Ren Chen ,  Ming Hung Tseng ,  Yi-Jen Lai

发明人： Yu-Ren Chen ,  Ming Hung Tseng ,  Yi-Jen Lai

IPC分类号： H01L23/485 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.

摘要翻译： 公开了半导体器件，封装方法和结构。 在一个实施例中，半导体器件包括具有周边区域和中心区域的表面的集成电路管芯。 在周边区域中的集成电路管芯的表面上设置有多个突起。 间隔件设置在中心区域的集成电路管芯的表面上。

公开(公告)号：US08193639B2

公开(公告)日：2012-06-05

申请号：US12750468

申请日：2010-03-30

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L23/485

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

摘要翻译： 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

公开(公告)号：US20110006416A1

公开(公告)日：2011-01-13

申请号：US12791127

申请日：2010-06-01

申请人： Ming Hung TSENG ,  Young-Chang LIEN ,  Chen-Shien CHEN ,  Chen-Cheng KUO

发明人： Ming Hung TSENG ,  Young-Chang LIEN ,  Chen-Shien CHEN ,  Chen-Cheng KUO

IPC分类号： H01L23/488 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.

摘要翻译： 提供一种用于形成金属柱凸块结构的方法。 在一个实施例中，在半导体衬底上形成钝化层，并且在钝化层上方形成导电层。 在导电层之上设置图案化和蚀刻的光致抗蚀剂层，光致抗蚀剂层在其中限定至少一个开口。 金属层沉积在至少一个开口中。 光致抗蚀剂层的一部分沿着光致抗蚀剂层和金属层之间的一个或多个界面被蚀刻以形成空腔。 焊料材料沉积在至少一个开口中，焊料材料填充空腔和金属层上方的开口的一部分。 去除残留的光致抗蚀剂层和未形成在铜层之下的导电层。 然后将焊料材料重新包覆以封装金属层。

公开(公告)号：US07180227B2

公开(公告)日：2007-02-20

申请号：US10759670

申请日：2004-01-16

申请人： Ming-Hung Tseng ,  Chin-Chih Chen ,  Tzu-Chan Wang ,  Wei-Shin Tien

发明人： Ming-Hung Tseng ,  Chin-Chih Chen ,  Tzu-Chan Wang ,  Wei-Shin Tien

IPC分类号： H01L41/053 ,  H01L41/113

CPC分类号： F16J15/064 ,  F16J15/32 ,  H01L41/1132

摘要： An o-ring sealing device, molded with an imbedded piezoelectric element, for use in vacuum systems. The imbedded element, of a circumferential length, has an oblong cross-sectional shape, the oblong shape having a pair of ends for externally connecting to a signal processor. The piezoelectric element is concentrically disposed and centrally placed within a mold cavity of a predetermined diameter. The cavity is filled with an elastic material fully encapsulating and insulating the piezoelectric element.

摘要翻译： 一种用于真空系统的O形圈密封装置，用嵌入式压电元件模制。 圆周长度的嵌入元件具有长方形横截面形状，长方形具有用于外部连接到信号处理器的一对端部。 压电元件同心地设置并居中放置在预定直径的模腔内。 空腔填充有完全封装并绝缘压电元件的弹性材料。

公开(公告)号：US20050156487A1

公开(公告)日：2005-07-21

申请号：US10759670

申请日：2004-01-16

申请人： Ming-Hung Tseng ,  Chin-Chih Chen ,  Tzu-Chan Wang ,  Wei-Shin Tien

发明人： Ming-Hung Tseng ,  Chin-Chih Chen ,  Tzu-Chan Wang ,  Wei-Shin Tien

IPC分类号： F16J15/06 ,  F16J15/32 ,  H01L21/00 ,  H01L41/08 ,  H01L41/113

CPC分类号： F16J15/064 ,  F16J15/32 ,  H01L41/1132

摘要： An o-ring sealing device, molded with an imbedded piezoelectric element, for use in vacuum systems. The imbedded element, of a circumferential length, has an oblong cross-sectional shape, the oblong shape having a pair of ends for externally connecting to a signal processor. The piezoelectric element is concentrically disposed and centrally placed within a mold cavity of a predetermined diameter. The cavity is filled with an elastic material fully encapsulating and insulating the piezoelectric element.

摘要翻译： 一种用于真空系统的O形圈密封装置，用嵌入式压电元件模制。 圆周长度的嵌入元件具有长方形横截面形状，长方形具有用于外部连接到信号处理器的一对端部。 压电元件同心地设置并居中放置在预定直径的模腔内。 空腔填充有完全封装并绝缘压电元件的弹性材料。

公开(公告)号：US20130093079A1

公开(公告)日：2013-04-18

申请号：US13276090

申请日：2011-10-18

申请人： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

发明人： Shang-Yun Tu ,  Yao-Chun Chuang ,  Ming Hung Tseng ,  Chen-Cheng Kuo ,  Chen-Shien Chen

IPC分类号： H01L23/498

CPC分类号： H01L24/16 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/061 ,  H01L2224/06132 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13541 ,  H01L2224/1405 ,  H01L2224/141 ,  H01L2224/16105 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

摘要： A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad.

公开(公告)号：US07919406B2

公开(公告)日：2011-04-05

申请号：US12791127

申请日：2010-06-01

申请人： Ming Hung Tseng ,  Young-Chang Lien ,  Chen-Shien Chen ,  Chen-Cheng Kuo

发明人： Ming Hung Tseng ,  Young-Chang Lien ,  Chen-Shien Chen ,  Chen-Cheng Kuo

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/13 ,  H01L2224/11462 ,  H01L2224/11472 ,  H01L2224/1182 ,  H01L2224/11849 ,  H01L2224/11906 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A method for forming a metal pillar bump structure is provided. In one embodiment, a passivation layer is formed over a semiconductor substrate and a conductive layer is formed over the passivation layer. A patterned and etched photoresist layer is provided above the conductive layer, the photoresist layer defining at least one opening therein. A metal layer is deposited in the at least one opening. Portions of the photoresist layer are etched along one or more interfaces between the photoresist layer and the metal layer to form cavities. A solder material is deposited in the at least one opening, the solder material filling the cavities and a portion of the opening above the metal layer. The remaining photoresist layer and the conductive layer not formed under the copper layer are removed. The solder material is then reflown to encapsulate the metal layer.

摘要翻译： 提供一种用于形成金属柱凸块结构的方法。 在一个实施例中，在半导体衬底上形成钝化层，并且在钝化层上方形成导电层。 在导电层之上设置图案化和蚀刻的光致抗蚀剂层，光致抗蚀剂层在其中限定至少一个开口。 金属层沉积在至少一个开口中。 光致抗蚀剂层的一部分沿着光致抗蚀剂层和金属层之间的一个或多个界面被蚀刻以形成空腔。 焊料材料沉积在至少一个开口中，焊料材料填充空腔和金属层上方的开口的一部分。 去除残留的光致抗蚀剂层和未形成在铜层之下的导电层。 然后将焊料材料重新包覆以封装金属层。

公开(公告)号：US08916969B2

公开(公告)日：2014-12-23

申请号：US13194606

申请日：2011-07-29

申请人： Yu-Ren Chen ,  Ming Hung Tseng ,  Yi-Jen Lai

发明人： Yu-Ren Chen ,  Ming Hung Tseng ,  Yi-Jen Lai

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L23/16 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC分类号： H01L23/562 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/06155 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16225 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00012

摘要： Semiconductor devices, packaging methods and structures are disclosed. In one embodiment, a semiconductor device includes an integrated circuit die with a surface having a peripheral region and a central region. A plurality of bumps is disposed on the surface of the integrated circuit die in the peripheral region. A spacer is disposed on the surface of the integrated circuit die in the central region.

摘要翻译： 公开了半导体器件，封装方法和结构。 在一个实施例中，半导体器件包括具有周边区域和中心区域的表面的集成电路管芯。 在周边区域中的集成电路管芯的表面上设置有多个突起。 间隔件设置在中心区域的集成电路管芯的表面上。

公开(公告)号：US08753971B2

公开(公告)日：2014-06-17

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/44

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。

公开(公告)号：US20120178252A1

公开(公告)日：2012-07-12

申请号：US13427430

申请日：2012-03-22

申请人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

发明人： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC分类号： H01L21/768

CPC分类号： H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

摘要： A method of forming an integrated circuit structure is provided. The method includes forming a metal pad at a major surface of a semiconductor chip, forming an under-bump metallurgy (UBM) over the metal pad such that the UBM and the metal pad are in contact, forming a dummy pattern at a same level as the metal pad, the dummy pattern formed of a same metallic material as the metal pad and electrically disconnected from the metal pad, and forming a metal bump over the UBM such that the metal bump is electrically connected to the UBM and no metal bump in the semiconductor chip is formed over the dummy pattern.

摘要翻译： 提供一种形成集成电路结构的方法。 该方法包括在半导体芯片的主表面上形成金属焊盘，在金属焊盘上形成凸块下冶金（UBM），使得UBM和金属焊盘接触，形成与 金属焊盘，由与金属焊盘相同的金属材料形成的虚拟图案，并与金属焊盘电气断开，并在UBM上形成金属凸块，使得金属凸块电连接到UBM，并且在金属焊盘中没有金属凸块 在虚拟图案上形成半导体芯片。