公开(公告)号：US20160322332A1

公开(公告)日：2016-11-03

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/522 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

Abstract translation: 一些特征涉及包括再分配部分，耦合到再分配部分的第一裸片，耦合到再分配部分的核心层以及封装第一裸片和核心层的封装层的封装。 再分配部分包括第一电介质层。 核心层具有比封装层更高的杨氏模量。 在一些实施方案中，芯层包括玻璃纤维（例如，芯层是玻璃增强介电层）。 在一些实施方案中，核心层具有约至少15吉帕斯卡（Gpa）的杨氏模量。 在一些实施方案中，第一管芯包括前侧和后侧，其中第一管芯的前侧连接到再分配部分。 在一些实施方案中，第一电介质层是可光致成像电介质（PID）层。

公开(公告)号：US09484327B2

公开(公告)日：2016-11-01

申请号：US13833921

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Marcus Bernard Hsu ,  David Fraser Rae

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L25/03 ,  H01L25/10 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: To achieve a package-on-package having an advantageously reduced height, a first package substrate has a window sized to receive a second package die. The first package substrate interconnects to the second package substrate through a plurality of package-to-package interconnects such that the first and second substrates are separated by a gap. The second package die has a thickness greater than the gap such that the second package die is at least partially disposed within the first package substrate's window.

Abstract translation: 为了实现具有有利地降低的高度的封装封装，第一封装衬底具有尺寸适于接收第二封装管芯的窗口。 第一封装衬底通过多个封装到封装互连而互连到第二封装衬底，使得第一和第二衬底被间隙隔开。 第二封装管芯的厚度大于间隙，使得第二封装管芯至少部分地设置在第一封装衬底的窗口内。

公开(公告)号：US10037941B2

公开(公告)日：2018-07-31

申请号：US14610876

申请日：2015-01-30

Applicant: QUALCOMM Incorporated

Inventor： Vladimir Noveski ,  Milind Pravin Shah ,  Rajneesh Kumar

IPC: H01L23/528 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5283 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03602 ,  H01L2224/03914 ,  H01L2224/05546 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/1111 ,  H01L2224/11334 ,  H01L2224/11438 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16013 ,  H01L2224/16014 ,  H01L2224/16111 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2711 ,  H01L2224/27438 ,  H01L2224/29006 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81101 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2924/2064 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated device package that includes a die, a substrate, a fill and a conductive interconnect. The die includes a pillar, where the pillar has a first pillar width. The substrate (e.g., package substrate, interposer) includes a dielectric layer and a substrate interconnect (e.g., surface interconnect, embedded interconnect). The fill is located between the die and the substrate. The conductive interconnect is located within the fill. The conductive interconnect includes a first interconnect width that is about the same or less than the first pillar width. The conductive interconnect is coupled to the pillar and the substrate interconnect. The fill is a non-conductive photosensitive material. The fill is a photosensitive film. The substrate interconnect includes a second interconnect width that is equal or greater than the first pillar width. The conductive interconnect includes one of at least a paste, a solder and/or an enhanced solder comprising a polymeric material.

公开(公告)号：US09379090B1

公开(公告)日：2016-06-28

申请号：US14622346

申请日：2015-02-13

Applicant: QUALCOMM Incorporated

Inventor： Ahmer Raza Syed ,  Chin-Kwan Kim ,  Omar James Bchir ,  Milind Pravin Shah ,  Ryan David Lane

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L25/0655 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/145 ,  H01L23/36 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/32 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2224/81005 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2924/15158 ,  H01L2924/15333

Abstract: A semiconductor package for a side by side die configuration may include a substrate having a cavity, a bridge interposer positioned within the cavity and having an active side facing active sides of a first die and a second die and partially horizontally overlapping the first die and the second die to provide an interconnection between the first die and the second die, and a thermal element attached to backsides of the first die and the second die to provide a heat path and heat storage for the first die and the second die.

Abstract translation: 用于并排管芯构造的半导体封装可以包括具有空腔的衬底，位于空腔内的桥插入器，并且具有面向第一管芯和第二管芯的主动侧的有源侧，并且部分水平地与第一管芯重叠， 第二模具以提供第一模具和第二模具之间的互连，以及附接到第一模具和第二模具的背面的热元件，以为第一模具和第二模具提供热路径和热存储。

公开(公告)号：US09466578B2

公开(公告)日：2016-10-11

申请号：US14251518

申请日：2014-04-11

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Manuel Aldrete ,  Milind Pravin Shah

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L24/03 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/06 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0903 ,  H01L2224/0912 ,  H01L2924/12042 ,  H01L2924/381 ,  H01L2924/00

Abstract: Some novel features pertain to an integrated device that includes a substrate, a first via, and a first bump pad. The first via traverses the substrate. The first via has a first via dimension. The first bump pad is on a surface of the substrate. The first bump pad is coupled to the first via. The first bump pad has a first pad dimension that is equal or less then the first via dimension. In some implementations, the integrated device includes a second via and a second bump pad. The second via traverses the substrate. The second via has a second via dimension. The second bump pad is on the surface of the substrate. The second bump pad is coupled to the second via. The second bump pad has a second pad dimension that is equal or less then the second via dimension.

Abstract translation: 一些新颖的特征涉及包括基板，第一通孔和第一凸块焊盘的集成装置。 第一个通孔穿过基板。 第一个通孔具有第一通孔尺寸。 第一凸块焊盘位于基板的表面上。 第一碰撞焊盘耦合到第一通孔。 第一凸块焊盘具有等于或小于第一通孔尺寸的第一焊盘尺寸。 在一些实施方案中，集成器件包括第二通孔和第二凸点焊盘。 第二个通孔穿过基板。 第二通孔具有第二通孔尺寸。 第二凸点焊盘位于基板的表面上。 第二凸点焊盘耦合到第二通孔。 第二凸块焊盘具有等于或小于第二通孔尺寸的第二焊盘尺寸。

公开(公告)号：US20140322868A1

公开(公告)日：2014-10-30

申请号：US14328618

申请日：2014-07-10

Applicant: QUALCOMM Incorporated

Inventor： Omar James Bchir ,  Milind Pravin Shah ,  Houssam Wafic Jomaa ,  Manuel Aldrete ,  Chin-Kwan Kim

IPC: H01L23/00 ,  H05K1/09

CPC classification number: H01L24/06 ,  H01L21/563 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/03 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/10175 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81143 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/83192 ,  H05K1/092 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some implementations provide a semiconductor device that includes a die, an under bump metallization (UBM) structure coupled to the die, and a barrier layer. The UBM structure has a first oxide property. The barrier layer has a second oxide property that is more resistant to oxide removal from a flux material than the first oxide property of the UBM structure. The barrier layer includes a top portion, a bottom portion and a side portion. The top portion is coupled to the UBM structure, and the side portion is substantially oxidized.

Abstract translation: 一些实施方案提供了一种半导体器件，其包括管芯，耦合到管芯的凹凸金属化（UBM）结构和阻挡层。 UBM结构具有第一氧化物性质。 阻挡层具有比UBM结构的第一氧化物性质更能抵抗从焊剂材料中去除氧化物的第二氧化物性质。 阻挡层包括顶部，底部和侧部。 顶部连接到UBM结构，并且侧部被基本氧化。

公开(公告)号：US09806063B2

公开(公告)日：2017-10-31

申请号：US14699863

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Vladimir Noveski ,  Jie Fu ,  Ahmer Raza Syed ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/16 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L21/56 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/56 ,  H01L21/568 ,  H01L21/768 ,  H01L23/16 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Some features pertain to a package that includes a redistribution portion, a first die coupled to the redistribution portion, a core layer coupled to the redistribution portion, and an encapsulation layer encapsulating the first die and the core layer. The redistribution portion includes a first dielectric layer. The core layer has a higher Young's Modulus than the encapsulation layer. In some implementations, the core layer includes a glass fiber (e.g., core layer is a glass reinforced dielectric layer). In some implementations, the core layer has a Young's Modulus of about at least 15 gigapascals (Gpa). In some implementations, the first die includes a front side and a back side, where the front side of the first die is coupled to the redistribution portion. In some implementations, the first dielectric layer is a photo imageable dielectric (PID) layer.

公开(公告)号：US09601435B2

公开(公告)日：2017-03-21

申请号：US14603166

申请日：2015-01-22

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  David Fraser Rae ,  Rajneesh Kumar ,  Milind Pravin Shah ,  Omar James Bchir

IPC: H01L23/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/16 ,  H01L23/13 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/29006 ,  H01L2224/29007 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/32227 ,  H01L2224/73253 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2224/92 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/19105 ,  H01L2224/81 ,  H01L2224/27 ,  H01L2224/83 ,  H01L2924/00014

Abstract: A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.

公开(公告)号：US20140227835A1

公开(公告)日：2014-08-14

申请号：US14255349

申请日：2014-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： Omar James Bchir ,  Milind Pravin Shah ,  Sashidhar Movva

IPC: H01L21/56 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/92125 ,  H01L2924/01057 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.

Abstract translation: 用于制造封装集成电路的背面模具配置（BSMC）工艺包括将模具化合物施加到与附接模具相对的封装基板的一侧。 将模具化合物沉积在电介质（例如光致抗蚀剂）上。 在将模具连接到包装基板上以暴露包装基板的接触垫之后，模制化合物和电介质被图案化。 在模制化合物和电介质图案化之后，封装连接通过模具化合物和电介质耦合到接触垫。 围绕包装连接的模具化合物减少处理期间包装基材的翘曲。 此外，在连接芯片之后对电介质进行图案化提高了封装连接的可靠性。

公开(公告)号：US09768108B2

公开(公告)日：2017-09-19

申请号：US14859318

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Jie Fu ,  Chin-Kwan Kim ,  Manuel Aldrete ,  Milind Pravin Shah ,  Dwayne Richard Shirley

IPC: H01L23/02 ,  H01L23/498 ,  H01L21/48 ,  H01L23/538 ,  H01L25/10

CPC classification number: H01L23/49894 ,  H01L21/4846 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/5389 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: An integrated circuit package includes a substrate/interposer assembly having a plurality of conductive contacts and a plurality of conductive posts, such as copper posts, electrically coupled to at least some of the conductive contacts in the substrate/interposer assembly. The conductive posts are surrounded by a protective dielectric, such as a photoimageable dielectric (PID). An integrated circuit die may be disposed on the substrate/interposer assembly within an interior space surrounded by the dielectric. An additional integrated circuit die may be provided in a package-on-package (POP) configuration.