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    Wafer edge conditioning for thinned wafers
    91.
    发明授权
    Wafer edge conditioning for thinned wafers 有权
    用于薄晶片的晶圆边缘调节

    公开(公告)号：US09105465B2

    公开(公告)日：2015-08-11

    申请号：US13053803

    申请日：2011-03-22

    Applicant: Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    Inventor： Timothy Harrison Daubenspeck ,  Jeffrey P. Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Timothy Dooling Sullivan

    IPC: H01L29/02 ,  H01L21/02

    CPC classification number: H01L21/02021

    Abstract: The present invention relates to a method for minimizing breakage of wafers during or after a wafer thinning process. A method of forming a rounded edge to the portion of a wafer remaining after surface grinding process is provided. The method comprises providing a semiconductor wafer having an edge and forming a recess in the edge of the wafer using any suitable mechanical or chemical process. The method further comprises forming a substantially continuous curved shape for at least the edge of the wafer located above the recess. Advantageously, the shape of the wafer is formed prior to the backside grind process to prevent problems caused by the otherwise presence of a sharp edge during the backside grind process.

    Abstract translation: 本发明涉及一种在晶圆薄化过程中或之后使晶片断裂最小化的方法。 提供了在表面研磨处理之后残留的晶片部分形成圆形边缘的方法。 该方法包括提供具有边缘的半导体晶片，并且使用任何合适的机械或化学过程在晶片的边缘中形成凹陷。 该方法还包括形成至少位于凹部上方的晶片的边缘的基本连续的弯曲形状。 有利地，在背面研磨处理之前形成晶片的形状，以防止在背面研磨过程期间另外存在锋利边缘引起的问题。

    3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts
    94.
    发明授权
    3-dimensional integrated circuit testing using MEMS switches with tungsten cone contacts 有权
    使用具有钨锥触点的MEMS开关的三维集成电路测试

    公开(公告)号：US08791712B2

    公开(公告)日：2014-07-29

    申请号：US13364345

    申请日：2012-02-02

    Applicant: John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    Inventor： John J. Ellis-Monaghan ,  Jeffrey P. Gambino ,  Kirk D. Peterson ,  Jed H. Rankin

    IPC: G01R1/067

    CPC classification number: G01R1/06727 ,  B81B2203/0118 ,  B81C1/00111 ,  G01R1/06738 ,  G01R1/06744 ,  G01R1/07342 ,  G01R3/00 ,  H01L21/76804 ,  H01L21/76885 ,  H01L22/14 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A test system for testing a multilayer 3-dimensional integrated circuit (IC), where two separate layers of IC circuits are temporarily connected in order to achieve functionality, includes a chip under test with a first portion of the 3-dimensional IC, and a test probe chip with a second portion of the 3-dimensional IC and micro-electrical-mechanical system (MEMS) switches that selectively complete functional circuits between the first portion of the 3-dimensional IC in a first IC layer to circuits within the second portion of the 3-dimensional IC in a second IC layer. The MEMS switches include tungsten (W) cone contacts, which make the selective electrical contacts between circuits of the chip under test and the test probe chip and which are formed using a template of graded borophosphosilicate glass (BPSG).

    Abstract translation: 一种用于测试多层三维集成电路（IC）的测试系统，其中临时连接两个独立的IC电路层以实现功能性，包括具有三维IC的第一部分的被测芯片，以及 测试探针芯片，其具有第三部分的IC和微机电系统（MEMS）开关，其选择性地完成第一IC层中的第三部分的第三部分之间的功能电路和第二部分内的电路 的三维IC在第二IC层中。 MEMS开关包括钨（W）锥形触点，其使得被测芯片的电路和测试探针芯片之间的选择性电接触，并且使用梯度硼磷硅酸盐玻璃（BPSG）的模板形成。

    Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics
    95.
    发明授权
    Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics 有权
    锗光电探测器肖特基接触与CMOS和Si纳米光子学一体化

    公开(公告)号：US08765502B2

    公开(公告)日：2014-07-01

    申请号：US13561177

    申请日：2012-07-30

    Applicant: Solomon Assefa ,  Jeffrey P. Gambino ,  Steven M. Shank

    Inventor： Solomon Assefa ,  Jeffrey P. Gambino ,  Steven M. Shank

    IPC: H01L21/00 ,  H01L35/34 ,  H01L51/50

    CPC classification number: H01L27/146 ,  H01L27/1443 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/1808 ,  H01L35/34 ,  H01L51/50 ,  Y02E10/50

    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

    Abstract translation: 形成具有光电检测器件和CMOS器件的集成光子半导体结构的方法可以包括在光电检测器器件上沉积电介质堆叠，使得电介质堆叠封装光电检测器。 电介质堆叠中的开口蚀刻到光电检测器的有源区域的区域的上表面。 第一金属层经由开口直接沉积在有源区域的区域的上表面上，使得第一金属层可以覆盖有源区域的区域。 在相同的掩模级内，包括第二金属层的多个触点位于第一金属层上和CMOS器件上。 第一金属层将活性区域与第二金属层和光电检测器的有源区域之间的金属混合的发生隔离。

    Method of fabricating photoconductor-on-active pixel device
    96.
    发明授权
    Method of fabricating photoconductor-on-active pixel device 有权
    制造感光体活性像素装置的方法

    公开(公告)号：US08753917B2

    公开(公告)日：2014-06-17

    申请号：US12967625

    申请日：2010-12-14

    Applicant: Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    Inventor： Jeffrey P. Gambino ,  Robert K. Leidy ,  Richard J. Rassel

    IPC: H01L31/112

    CPC classification number: H01L31/105 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14665 ,  H01L27/14687

    Abstract: A design structure embodied in a machine readable medium used in a design process includes a first dielectric layer disposed on an intermediary layer, a first conductive pad portion and a first interconnect portion disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, a first capping layer disposed on the first interconnect portion and a portion of the first conductive pad portion, a second capping layer disposed on the first capping layer and a portion of the second dielectric layer, an n-type doped silicon layer disposed on the second capping layer and the first conductive pad portion, an intrinsic silicon layer disposed on the n-type doped silicon layer, and a p-type doped silicon layer disposed on the intrinsic silicon layer.

    Abstract translation: 体现在设计过程中使用的机器可读介质中的设计结构包括设置在中间层上的第一介电层，设置在第一介电层上的第一导电焊盘部分和第一互连部分，设置在第一介电层上的第二介电层 电介质层，设置在第一互连部分上的第一覆盖层和第一导电焊盘部分的一部分，设置在第一覆盖层上的第二封盖层和第二介电层的一部分，设置n型掺杂硅层 在第二覆盖层和第一导电焊盘部分上，设置在n型掺杂硅层上的本征硅层和设置在本征硅层上的p型掺杂硅层。

    GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS
    98.
    发明申请
    GERMANIUM PHOTODETECTOR SCHOTTKY CONTACT FOR INTEGRATION WITH CMOS AND Si NANOPHOTONICS 有权
    锗与光电子器件肖特基接触

    公开(公告)号：US20140027826A1

    公开(公告)日：2014-01-30

    申请号：US13561177

    申请日：2012-07-30

    Applicant: Solomon Assefa ,  Jeffrey P. Gambino ,  Steven M. Shank

    Inventor： Solomon Assefa ,  Jeffrey P. Gambino ,  Steven M. Shank

    IPC: H01L27/14 ,  G06F17/50 ,  H01L31/18

    CPC classification number: H01L27/146 ,  H01L27/1443 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/1808 ,  H01L35/34 ,  H01L51/50 ,  Y02E10/50

    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

    Abstract translation: 形成具有光电检测器件和CMOS器件的集成光子半导体结构的方法可以包括在光电检测器器件上沉积电介质堆叠，使得电介质堆叠封装光电检测器。 电介质堆叠中的开口蚀刻到光电检测器的有源区域的区域的上表面。 第一金属层经由开口直接沉积在有源区域的区域的上表面上，使得第一金属层可以覆盖有源区域的区域。 在相同的掩模级内，包括第二金属层的多个触点位于第一金属层上和CMOS器件上。 第一金属层将活性区域与第二金属层和光电检测器的有源区域之间的金属混合的发生隔离。

    Structure and method for reducing vertical crack propagation
    100.
    发明授权
    Structure and method for reducing vertical crack propagation 有权
    减少垂直裂纹扩展的结构和方法

    公开(公告)号：US08604618B2

    公开(公告)日：2013-12-10

    申请号：US13239533

    申请日：2011-09-22

    Applicant: Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

    Inventor： Edward C. Cooney, III ,  Jeffrey P. Gambino ,  Zhong-Xiang He ,  Xiao Hu Liu ,  Thomas L. McDevitt ,  Gary L. Milo ,  William J. Murphy

    IPC: H01L23/485 ,  H01L21/3205

    CPC classification number: H01L21/76802 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

    Abstract translation: 半导体器件及其制造方法包括在绝缘体上的垂直堆叠的层。 每个层包括第一介电绝缘体部分，嵌入在第一介电绝缘体部分内的第一金属导体，覆盖第一金属导体的第一氮化物帽，第二电介质绝缘体部分，嵌入在第二介电绝缘体部分内的第二金属导体 以及覆盖所述第二金属导体的第二氮化物帽。 第一和第二金属导体形成第一垂直堆叠的导体层和第二垂直堆叠的导体层。 第一垂直堆叠的导体层靠近第二垂直堆叠的导体层，并且至少一个气隙位于第一垂直堆叠的导体层和第二垂直堆叠的导体层之间。 上半导体层覆盖第一垂直堆叠的导体层，气隙和第二多个垂直堆叠的导体层。

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