公开(公告)号：US09792061B2

公开(公告)日：2017-10-17

申请号：US15334484

申请日：2016-10-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael T. Benhase ,  Lokesh M. Gupta ,  Warren K. Stanley

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/0875

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/065 ,  G06F3/067 ,  G06F3/0689 ,  G06F12/0875 ,  G06F2212/452

Abstract: For efficient cache management of multi-target peer-to-peer remote copy (PPRC) modified sectors bitmap in a computing storage environment a multiplicity of PPRC modified sectors bitmaps are dynamically managed by placing the multiplicity of PPRC modified sectors bitmaps into slots of bind segments. One of the multiplicity of PPRC modified sectors bitmaps is set in one of the plurality of slots. Techniques are used depending on whether it is determined that one of the bind segments in the list of bind segments does not contain the free one of the multiplicity of slots.

公开(公告)号：US20170293486A1

公开(公告)日：2017-10-12

申请号：US15092915

申请日：2016-04-07

Applicant: Imagination Technologies Limited

Inventor： Ranjit J. Rozario ,  Andrew F. Glew ,  Sanjay Patel ,  James Robinson ,  Sudhakar Ranganathan

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

公开(公告)号：US09785565B2

公开(公告)日：2017-10-10

申请号：US14749955

申请日：2015-06-25

Applicant: MicroUnity Systems Engineering, Inc.

Inventor： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC: G06F12/08 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F9/3016 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/3895 ,  G06F2212/452

Abstract: Expandably wide operations are disclosed in which operands wider than the data path between a processor and memory are used in executing instructions. The expandably wide operands reduce the influence of the characteristics of the associated processor in the design of functional units performing calculations, including the width of the register file, the processor clock rate, the exception subsystem of the processor, and the sequence of operations in loading and use of the operand in a wide cache memory.

公开(公告)号：US20170286119A1

公开(公告)日：2017-10-05

申请号：US15087069

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Rami Mohammad Al Sheikh ,  Raguram Damodaran

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30043 ,  G06F9/3832 ,  G06F9/3848 ,  G06F12/0875 ,  G06F2212/452

Abstract: Aspects disclosed in the detailed description include providing load address predictions using address prediction tables based on load path history in processor-based systems. In one aspect, a load address prediction engine provides a load address prediction table containing multiple load address prediction table entries. Each load address prediction table entry includes a predictor tag field and a memory address field for a load instruction. The load address prediction engine generates a table index and a predictor tag based on an identifier and a load path history for a detected load instruction. The table index is used to look up a corresponding load address prediction table entry. If the predictor tag matches the predictor tag field of the load address prediction table entry corresponding to the table index, the memory address field of the load address prediction table entry is provided as a predicted memory address for the load instruction.

公开(公告)号：US09779028B1

公开(公告)日：2017-10-03

申请号：US15088302

申请日：2016-04-01

Applicant: Cavium, Inc.

Inventor： Shubhendu Sekhar Mukherjee ,  Mike Bertone

IPC: G06F12/06 ,  G06F12/1045 ,  G06F12/1027 ,  G06F12/1036 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/0811 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/152 ,  G06F2212/452 ,  G06F2212/651 ,  G06F2212/682 ,  G06F2212/683

Abstract: Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs) consisting of fewer than all VAs associated with a first set of translation context (TC) values, searching VA-indexed structure(s) to find and invalidate any entries that correspond to a VA in the subset; in response to determining that a second IM applies to all VAs associated with a second set of TC values and that no entry exists in invalidation-tracking structure(s) corresponding to the second set, bypassing searching any VA-indexed structure(s); and in response to determining that a third IM applies to all VAs associated with a third set of TC values and that at least one entry exists in the invalidation-tracking structure(s) corresponding to the third set, storing invalidation information in the invalidation-tracking structure(s) to invalidate the third set and delaying searching any VA-indexed structure(s).

公开(公告)号：US09772779B2

公开(公告)日：2017-09-26

申请号：US15098574

申请日：2016-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Luigi Pilolli

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C7/10 ,  G06F13/16 ,  G11C16/06 ,  G06F12/0875 ,  G06F12/0893

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/1668 ,  G06F2212/2022 ,  G06F2212/452 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/16 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/06 ,  G11C16/10 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.

公开(公告)号：US09766680B2

公开(公告)日：2017-09-19

申请号：US15162745

申请日：2016-05-24

Applicant: L. Pierre de Rochemont

Inventor： L. Pierre de Rochemont

IPC: G06F12/00 ,  G06F1/32 ,  G06F1/26 ,  H01L21/762 ,  H01L21/00 ,  H01L27/02 ,  H01L21/84 ,  H01L25/065 ,  H01L25/16 ,  G06F9/30 ,  G06F9/38 ,  G06F12/1009 ,  G06F13/16 ,  G06F13/24 ,  G11C7/10 ,  G06F1/28 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80

CPC classification number: G06F1/3203 ,  G06F1/26 ,  G06F1/28 ,  G06F1/324 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0685 ,  G06F9/3001 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/3802 ,  G06F12/0815 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1009 ,  G06F13/1605 ,  G06F13/1673 ,  G06F13/1689 ,  G06F13/24 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/621 ,  G06F2212/65 ,  G06F2213/0038 ,  G11C7/1072 ,  H01L21/00 ,  H01L21/76229 ,  H01L21/84 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/3011 ,  Y02D10/14 ,  Y02D10/151 ,  Y10S257/00 ,  H01L2924/00

Abstract: A hybrid system-on-chip provides a plurality of memory and processor die mounted on a semiconductor carrier chip that contains a fully integrated power management system that switches DC power at speeds that match or approach processor core clock speeds, thereby allowing the transfer of data between off-chip physical memory and processor die.

公开(公告)号：US20170262287A1

公开(公告)日：2017-09-14

申请号：US13824013

申请日：2011-09-16

Applicant: Mohammad Abdallah

Inventor： Mohammad Abdallah

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

CPC classification number: G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

公开(公告)号：US09761634B2

公开(公告)日：2017-09-12

申请号：US14848164

申请日：2015-09-08

Applicant: SK hynix Inc.

Inventor： Sung-Joon Yoon

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G06F12/0875

CPC classification number: H01L27/222 ,  G06F12/0875 ,  G06F2212/452 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: This patent document provides an electronic device capable of improving the characteristics of a variable resistance element. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a variable resistance element capable of being included in the semiconductor memory, and including a fixed layer, a tunnel barrier layer, and a variable layer laminated therein, wherein the variable resistance element is capable of allowing a slope of a graph of a switching current density as a function of an external magnetic field to be proportional to the square of “H/Hk” when the magnetization directions of the fixed layer and the variable layer are switched from a parallel state to an antiparallel state. In accordance with the electronic device of this patent document, the characteristics of the variable resistance element can be improved.

公开(公告)号：US09753855B2

公开(公告)日：2017-09-05

申请号：US14410615

申请日：2013-06-25

Applicant: Shanghai XinHao Micro Electronics Co. Ltd.

Inventor： Chenghao Kenneth Lin

IPC: G06F12/08 ,  G06F12/0875 ,  G06F12/0811

CPC classification number: G06F12/0875 ,  G06F12/0811 ,  G06F2212/452 ,  Y02D10/13

Abstract: A method is provided for facilitating operation of a processor core coupled to a first memory containing executable instructions, a second memory faster than the first memory and a third memory faster than the second memory. The method includes examining instructions being filled from the second memory to the third memory, extracting instruction information containing at least branch information; creating a plurality of tracks based on the extracted instruction information; filling at least one or more instructions that possibly be executed by the processor core based on one or more tracks from a plurality of instruction tracks from the first memory to the second memory; filling at least one or more instructions based on one or more tracks from the plurality of tracks from the second memory to the third memory before the processor core executes the instructions, such that the processor core fetches the instructions from the third memory.