公开(公告)号：US10135427B2

公开(公告)日：2018-11-20

申请号：US15829693

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Brian S. Leibowitz ,  Qi Lin

IPC: H03K5/08 ,  H03K3/013 ,  G11C7/02 ,  H03K5/153 ,  H04L25/49 ,  H04L25/06 ,  H04L25/03

Abstract: A system for communicating information between circuits is described. A transmit circuit provides pulse-amplitude-modulation (PAM) signals via a communication channel to a receiver. A circuit in the receiver determines digital values from the received signals using a time-varying threshold voltage, which varies during the bit-time. This approach may compensate for inter-symbol interference (ISI) to increase the voltage and timing margins of the system.

公开(公告)号：US10044530B2

公开(公告)日：2018-08-07

申请号：US15178493

申请日：2016-06-09

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L25/03 ,  G06F13/38

Abstract: An integrated circuit (IC) memory controller includes receiver circuitry to receive read data from a memory. The receiver circuitry includes equalization circuitry having at least one tap to apply data level equalization to the read data, and a tap weight adapter circuit. The tap weight adapter circuit adaptively generates a data level tap weight corresponding to the data level equalization from an edge analysis of previously received read data.

公开(公告)号：US20180198455A1

公开(公告)日：2018-07-12

申请号：US15720401

申请日：2017-09-29

Applicant: Rambus Inc.

Inventor： Marko Aleksic ,  Brian S. Leibowitz

IPC: H03L7/24 ,  H03L7/099 ,  H03L7/081

CPC classification number: H03L7/24 ,  H03K5/26 ,  H03K2005/00286 ,  H03L7/081 ,  H03L7/099 ,  H03L7/0995

Abstract: Methods and apparatuses featuring an injection-locked oscillator (ILO) are described. In some embodiments, an ILO can have multiple injection points and a free-running frequency that is capable of being adjusted based on a control signal. In some embodiments, each injection point of an ILO can correspond to a phase tuning range. In some embodiments, a circuit can include circuitry to detect a phase boundary between two adjacent phase tuning ranges. In some embodiments, a circuit can use the detected phase boundary to switch between the two adjacent phase tuning ranges.

公开(公告)号：US09900189B2

公开(公告)日：2018-02-20

申请号：US15233557

申请日：2016-08-10

Applicant: Rambus Inc.

Inventor： Jared L. Zerbe ,  Fariborz Assaderaghi ,  Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Qi Lin

IPC: H04L25/03

CPC classification number: H04L25/03343 ,  H04L25/03057 ,  H04L25/0307 ,  H04L25/03885 ,  H04L2025/03356 ,  H04L2025/03433 ,  H04L2025/03617

Abstract: A transceiver architecture supports high-speed communication over a signal lane that extends between a high-performance integrated circuit (IC) and one or more relatively low-performance ICs employing less sophisticated transmitters and receivers. The architecture compensates for performance asymmetry between ICs communicating over a bidirectional lane by instantiating relatively complex transmit and receive equalization circuitry on the higher-performance side of the lane. Both the transmit and receive equalization filter coefficients in the higher-performance IC may be adaptively updated based upon the signal response at the receiver of the higher-performance IC.

公开(公告)号：US20180047436A1

公开(公告)日：2018-02-15

申请号：US15623261

申请日：2017-06-14

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C5/04 ,  G11C5/06 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/02 ,  G11C7/10

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

公开(公告)号：US20170133070A1

公开(公告)日：2017-05-11

申请号：US15390681

申请日：2016-12-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Brian S. Leibowitz ,  Wayne Frederick Ellis ,  Akash Bansal ,  John Welsford Brooks ,  Kishore Ven Kasamsetty

IPC: G11C8/18 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10

CPC classification number: G11C8/18 ,  G06F13/161 ,  G06F13/1647 ,  G06F13/1657 ,  G06F13/4234 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1072 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: In a multirank memory system in which the clock distribution trees of each rank are permitted to drift over a wide range (e.g., low power memory systems), the fine-interleaving of commands between ranks is facilitated through the use of techniques that cause each addressed rank to properly sample commands intended for that rank, notwithstanding the drift. The ability to perform such “microthreading” provides for substantially enhanced memory capacity without sacrificing the performance of single rank systems. This disclosure provides methods, memory controllers, memory devices and system designs adapted to these ends.

公开(公告)号：US20160344577A1

公开(公告)日：2016-11-24

申请号：US15165134

申请日：2016-05-26

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Bruno W. Garlepp

IPC: H04L25/03 ,  H04L5/00 ,  H04J11/00

CPC classification number: H04L25/03057 ,  G01R31/31709 ,  G01R31/31711 ,  H04J11/0023 ,  H04L1/20 ,  H04L1/241 ,  H04L1/242 ,  H04L1/244 ,  H04L5/006 ,  H04L7/033 ,  H04L25/03146

Abstract: Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments allows feedback timing to be adjusted independent of the sample timing to measure the effects of some forms of phase misalignment and jitter.

Abstract translation: 描述了数字接收机边缘测试的方法和电路。 这些方法和电路可以防止误差响应于错误接收的数据而崩溃，并且因此可以用于采用历史数据的接收机来减少符号间干扰（ISI）。 一些实施例允许独立于采样定时来调整反馈定时以测量某些形式的相位未对准和抖动的影响。

公开(公告)号：US09465961B2

公开(公告)日：2016-10-11

申请号：US14098628

申请日：2013-12-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Brian S. Leibowitz ,  Pradeep Batra ,  Trung Am Diep

IPC: G06F12/14 ,  G06F21/85 ,  G06F21/78 ,  G09C1/00 ,  H04L9/06 ,  H04L9/12

CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/065 ,  H04L9/12 ,  H04L2209/12 ,  H04L2209/56

Abstract: Described are systems and method for protecting data and instructions shared over a memory bus and stored in memory. Independent and separately timed stream ciphers for write and read channels allow timing variations between write and read transactions. Data and instructions can be separately encrypted prior to channel encryption to further secure the information. pad generators and related cryptographic circuits are shared for read and write data, and to secure addresses. The cryptographic circuits can support variable data widths, and in some embodiments memory devices incorporate security circuitry that can implement a shared-key algorithm using repurposed memory circuitry.

Abstract translation: 描述了用于保护在存储器总线上共享并存储在存储器中的数据和指令的系统和方法。 用于写入和读取通道的独立且单独定时的流密码允许写入和读取事务之间的时序变化。 数据和指令可以在通道加密之前单独加密，以进一步保护信息。 垫片发生器和相关的加密电路被共享用于读取和写入数据，并且保护地址。 加密电路可以支持可变数据宽度，并且在一些实施例中，存储器设备包括可以使用重用存储器电路来实现共享密钥算法的安全电路。

公开(公告)号：US09391816B2

公开(公告)日：2016-07-12

申请号：US14462561

申请日：2014-08-19

Applicant: Rambus Inc.

Inventor： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

IPC: H03H7/30 ,  H04B1/10 ,  H04L27/06 ,  H04L7/00 ,  H04L25/03

CPC classification number: H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.

Abstract translation: 公开了一种方法。 该方法包括对数据信号的预期边沿时间具有电压值的数据信号进行采样。 产生第一个α值，并根据电压值生成第二个alpha值。 数据信号通过第一个alpha值进行调整，以得到第一个调整后的信号。 数据信号通过第二α值进行调整，以得到第二调整信号。 第一调整后的信号被采样以输出第一数据值，而第二调整信号被采样以输出第二数据值。 作为先前接收的数据值的函数，在第一数据值和第二数据值之间进行选择，以确定接收到的数据值。

公开(公告)号：US09262342B2

公开(公告)日：2016-02-16

申请号：US14133383

申请日：2013-12-18

Applicant: RAMBUS INC.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F12/00 ,  G06F12/14 ,  G06F21/79 ,  G06F12/10

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。