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    SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS
    121.
    发明申请
    SEMICONDUCTOR DEVICES WITH UNDERFILL CONTROL FEATURES, AND ASSOCIATED SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190371755A1

    公开(公告)日：2019-12-05

    申请号：US16541449

    申请日：2019-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Suresh Yeruva ,  Kyle K. Kirby ,  Owen R. Fay ,  Sameer S. Vadhavkar

    IPC: H01L23/00 ,  H01L23/24 ,  H01L21/56

    Abstract: Semiconductor devices with underfill control features, and associated systems and methods. A representative system includes a substrate having a substrate surface and a cavity in the substrate surface, and a semiconductor device having a device surface facing toward the substrate surface. The semiconductor device further includes at least one circuit element electrically coupled to a conductive structure. The conductive structure is electrically connected to the substrate, and the semiconductor device further has a non-conductive material positioned adjacent the conductive structure and aligned with the cavity of the substrate. An underfill material is positioned between the substrate and the semiconductor device. In other embodiments, in addition to or in lieu of the con-conductive material, a first conductive structure is connected within the cavity, and a second conductive structure connected outside the cavity. The first conductive structure extends away from the device surface a greater distance than does the second conductive structure.

    PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS
    122.
    发明申请
    PROXIMITY COUPLING INTERCONNECT PACKAGING SYSTEMS AND METHODS 审中-公开

    公开(公告)号：US20190296003A1

    公开(公告)日：2019-09-26

    申请号：US16440727

    申请日：2019-06-13

    Applicant: Micron Technology, Inc.

    Inventor： Rich Fogal ,  Owen R. Fay

    IPC: H01L25/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L21/54 ,  H01L21/48 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.

    Interconnect structures for preventing solder bridging, and associated systems and methods
    123.
    发明授权
    Interconnect structures for preventing solder bridging, and associated systems and methods 有权

    公开(公告)号：US10297561B1

    公开(公告)日：2019-05-21

    申请号：US15853512

    申请日：2017-12-22

    Applicant: Micron Technology, Inc.

    Inventor： Kyle S. Mayer ,  Owen R. Fay

    IPC: H01L23/00 ,  H01L21/288

    Abstract: Semiconductor dies having interconnect structures formed thereon, and associated systems and methods, are disclosed herein. In one embodiment, an interconnect structure includes a conductive material electrically coupled to an electrically conductive contact of a semiconductor die. The conductive material includes a first portion vertically aligned with the conductive contact, and a second portion that extends laterally away from the conductive contact. A solder material is disposed on the second portion of the interconnect structure such that the solder material is at least partially laterally offset from the conductive contact of the semiconductor die. In some embodiments, an interconnect structure can further include a containment layer that prevents wicking or other undesirable movement of the solder material during a reflow process.

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