公开(公告)号：US20080284000A1

公开(公告)日：2008-11-20

申请号：US11770451

申请日：2007-06-28

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L23/14 ,  H01L21/00

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US07442578B2

公开(公告)日：2008-10-28

申请号：US11507951

申请日：2006-08-21

Applicant: Tongbi Jiang ,  Curtis Hollingshead ,  Warren M. Farnworth

Inventor： Tongbi Jiang ,  Curtis Hollingshead ,  Warren M. Farnworth

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/29 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/05599

Abstract: Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by the microelectronic component, and an underfill layer covering at least a portion of the electrical couplers. The underfill layer comprises a binder and a plurality of electrically charged filler elements in the binder. The underfill layer can include a first zone having a first concentration of electrically charged filler elements and a second zone having a second concentration of electrically charged filler elements different than the first concentration.

Abstract translation: 本文公开了包括带电填充元件的底部填充化合物，具有底部填充化合物的微电子器件，包括带电荷的填料元件，以及在微电子器件上设置包含充电填充元素的底部填充剂的方法。 在一个实施例中，微电子器件包括微电子部件，由微电子部件承载的多个电耦合器以及覆盖电耦合器的至少一部分的底部填充层。 底部填充层包括粘合剂和粘合剂中的多个带电荷的填料元素。 底部填充层可以包括具有第一浓度的带电填充元件的第一区域和具有不同于第一浓度的带电荷填充元件的第二浓度的第二区域。

公开(公告)号：US20080251943A1

公开(公告)日：2008-10-16

申请号：US11734497

申请日：2007-04-12

Applicant: David J. Corisis ,  Tongbi Jiang

Inventor： David J. Corisis ,  Tongbi Jiang

IPC: H01L23/12 ,  H01L21/58

CPC classification number: H01L23/49827 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

Abstract translation: 公开了一种器件，其包括：芯片，其包括集成电路和耦合到管芯的插入器，所述插入器具有比所述管芯小的占地面积。 公开了一种方法，其包括将插入件可操作地耦合到包括集成电路的管芯，所述插入器具有比所述管芯更小的占地面积，以及用底部填充材料填充所述插入件与所述管芯之间的空间。

公开(公告)号：US07344061B2

公开(公告)日：2008-03-18

申请号：US10932471

申请日：2004-09-01

Applicant: Tsuyoshi Yamashita ,  Tongbi Jiang

Inventor： Tsuyoshi Yamashita ,  Tongbi Jiang

IPC: B23K31/02 ,  H01L23/52

CPC classification number: H01L24/10 ,  B23K1/0016 ,  B23K35/0244 ,  B23K35/025 ,  B23K35/262 ,  B23K35/3612 ,  B23K35/3613 ,  B23K35/3618 ,  B23K2101/40 ,  H01L23/488 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3489 ,  H05K2203/043 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599

Abstract: Aspects of the invention provide solder compositions which include two different fluxing agents. One of the fluxing agents promotes melting of a metal of the solder at a first activation temperature and the other fluxing agent promotes melting of the metal at a second activation temperature that is higher than the first activation temperature. This dual-flux solder may be used in manufacturing microelectronic components and microelectronic component assemblies. In one specific application, the solder may be used to manufacture a flip chip or other microelectronic component which includes self-fluxing solder balls. This can obviate the need to apply another flux composition to the solder balls prior to a subsequent component attach reflow operation.

Abstract translation: 本发明的方面提供了包括两种不同助熔剂的焊料组合物。 助熔剂之一促进在第一活化温度下焊接金属的熔化，另一种助熔剂促进金属在高于第一活化温度的第二活化温度下熔化。 这种双通量焊料可用于制造微电子部件和微电子部件组件。 在一个具体应用中，焊料可用于制造倒装芯片或其他包括自熔焊球的微电子部件。 这可以避免在随后的组件附着回流操作之前将另外的焊剂组合物应用于焊球。

公开(公告)号：US20070262436A1

公开(公告)日：2007-11-15

申请号：US11433015

申请日：2006-05-12

Applicant: Young Kweon ,  J. Brooks ,  Tongbi Jiang

Inventor： Young Kweon ,  J. Brooks ,  Tongbi Jiang

IPC: H01L23/28 ,  H01L21/66 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L22/20 ,  H01L23/3135 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Microelectronic devices and methods for manufacturing microelectronic devices are described herein. An embodiment of one such method includes attaching a plurality of singulated microelectronic dies to a removable support member with an active side of the individual dies facing toward the support member, depositing a flowable material onto the dies and a portion of the removable support member such that the flowable material covers a back side of the individual dies and is disposed between adjacent dies, and removing the support member from the active sides of the dies.

Abstract translation: 本文描述了用于制造微电子器件的微电子器件和方法。 一种这样的方法的实施例包括将多个单独的微电子管芯附接到可移除的支撑构件，其中各个模具的活动侧面向支撑构件，将可流动材料沉积到模具上以及可移除支撑构件的一部分，使得 可流动材料覆盖各个模具的背面并且设置在相邻模具之间，并且从模具的活动侧移除支撑构件。

公开(公告)号：US07268012B2

公开(公告)日：2007-09-11

申请号：US10931678

申请日：2004-08-31

Applicant: Tongbi Jiang ,  Li Li ,  William M. Hiatt

Inventor： Tongbi Jiang ,  Li Li ,  William M. Hiatt

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/48 ,  H01L23/28

CPC classification number: H01L21/486 ,  H01L21/4803 ,  H01L21/4846 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3114 ,  H01L23/49816 ,  H01L24/10 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/83005 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/0032 ,  H05K3/0052 ,  H05K3/0058 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2203/016 ,  H05K2203/0384 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods for creating redistribution layers for only selected dice, such as known good dice, to form relatively thin semiconductor component assemblies and packages, and the assemblies and packages created by the methods, are disclosed. A sacrificial layer is deposited on a support substrate. An etch stop layer having a lower etch is deposited on the sacrificial layer. Redistribution lines in a dielectric material are formed on the support substrate on the etch stop layer. Semiconductor dice, either singulated or at the wafer level, are connected to the redistribution lines. The assembly may be scribed to allow the sacrificial layer to be etched to enable removal of the semiconductor dice and associated redistribution layer from the support substrate. The etch stop layer is removed to allow access to the redistribution lines for conductive bumping.

Abstract translation: 公开了用于仅为所选择的骰子创建再分布层（例如已知的骰子）以形成相对薄的半导体元件组件和封装以及由该方法产生的组件和封装件的方法。 牺牲层沉积在支撑衬底上。 具有较低蚀刻的蚀刻停止层沉积在牺牲层上。 介电材料中的再分布线形成在蚀刻停止层上的支撑衬底上。 单片化或晶圆级的半导体管芯连接到再分配线。 可以对组件进行划线以允许蚀刻牺牲层，以便能够从支撑衬底去除半导体晶片和相关联的再分配层。 去除蚀刻停止层以允许进入用于导电凸起的再分配线。

公开(公告)号：US20070095280A1

公开(公告)日：2007-05-03

申请号：US11641523

申请日：2006-12-19

Applicant: Ed Schrock ,  Tongbi Jiang

Inventor： Ed Schrock ,  Tongbi Jiang

IPC: B05C13/02 ,  B05C13/00 ,  B05C11/02 ,  B05C21/00

CPC classification number: H01L24/83 ,  C09J5/06 ,  H01L23/49513 ,  H01L24/31 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/05599 ,  H01L2224/2919 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/83048 ,  H01L2224/83097 ,  H01L2224/8319 ,  H01L2224/83855 ,  H01L2224/85048 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A method for attaching a workpiece, for example a semiconductor die, to a workpiece holder, for example a lead frame die support, comprises the steps of interposing an uncured adhesive between the semiconductor die and the die support and preheating the adhesive from an ambient temperature to a preheat temperature of between about 150° C. and about 160° C. over a period of about 1.5 seconds. Next, the preheat temperature is maintained for about 1.5 seconds, then the adhesive is further heated to a temperature of between about 190° C. and about 200° C. over a period of about 1.0 second. The inventive method quickly cures the adhesive to secure the die to the support with acceptably low levels of voiding. An apparatus which may be adapted to perform the inventive method is further described.

Abstract translation: 用于将工件（例如半导体管芯）附接到工件保持器（例如引线框模具支撑件）上的方法包括以下步骤：在半导体管芯和管芯支撑件之间插入未固化的粘合剂，并从环境温度预热粘合剂 在约1.5秒的时间段内达到约150℃至约160℃的预热温度。 接下来，将预热温度保持约1.5秒，然后在约1.0秒的时间内将粘合剂进一步加热至约190℃至约200℃的温度。 本发明的方法快速固化粘合剂以将模具固定到具有可接受的低水平的空隙的支撑体上。 进一步描述可适于执行本发明方法的装置。

公开(公告)号：US20070082429A1

公开(公告)日：2007-04-12

申请号：US11538344

申请日：2006-10-03

Applicant: Tongbi Jiang

Inventor： Tongbi Jiang

IPC: H01L21/00

CPC classification number: H01L23/544 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.

Abstract translation: 本发明提供了制造积层单芯片或多芯片模块的技术。 在一个实施例中，这通过在衬底上的一个或多个预蚀刻空腔中分配管芯附着材料来实现。 然后通过在衬底上施加略微向下的压力将半导体管芯放置在包括管芯附接材料的每个预蚀刻腔体上，使得每个放置的半导体管芯的有源表面跨过衬底设置，并且进一步基本上与 基质。 然后通过固化管芯附着材料将半导体管芯固定到衬底上。 然后，在衬底和每个半导体管芯的有源表面上形成包括一个或多个交替层的电介质材料和金属化结构的微型电路板，以使半导体管芯互连。

公开(公告)号：US20070048900A1

公开(公告)日：2007-03-01

申请号：US11507951

申请日：2006-08-21

Applicant: Tongbi Jiang ,  Curtis Hollingshead ,  Warren Farnworth

Inventor： Tongbi Jiang ,  Curtis Hollingshead ,  Warren Farnworth

IPC: H01L21/00

CPC classification number: H01L21/563 ,  H01L23/295 ,  H01L24/29 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83191 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2224/05599

Abstract: Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of disposing underfill including electrically charged filler elements on microelectronic devices are disclosed herein. In one embodiment, a microelectronic device includes a microelectronic component, a plurality of electrical couplers carried by the microelectronic component, and an underfill layer covering at least a portion of the electrical couplers. The underfill layer comprises a binder and a plurality of electrically charged filler elements in the binder. The underfill layer can include a first zone having a first concentration of electrically charged filler elements and a second zone having a second concentration of electrically charged filler elements different than the first concentration.

Abstract translation: 本文公开了包括带电填充元件的底部填充化合物，具有底部填充化合物的微电子器件，包括带电荷的填料元件，以及在微电子器件上设置包含充电填充元素的底部填充剂的方法。 在一个实施例中，微电子器件包括微电子部件，由微电子部件承载的多个电耦合器以及覆盖电耦合器的至少一部分的底部填充层。 底部填充层包括粘合剂和粘合剂中的多个带电荷的填料元素。 底部填充层可以包括具有第一浓度的带电填充元件的第一区域和具有不同于第一浓度的带电荷填充元件的第二浓度的第二区域。

公开(公告)号：US07170184B2

公开(公告)日：2007-01-30

申请号：US10341610

申请日：2003-01-13

Applicant: Tongbi Jiang ,  Mike Connell ,  Li Li ,  Curtis Hollingshead

Inventor： Tongbi Jiang ,  Mike Connell ,  Li Li ,  Curtis Hollingshead

IPC: H01L23/02 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/83 ,  H01L21/67132 ,  H01L21/67144 ,  H01L24/32 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01023 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Methods are provided to improve the adhesive bonding of a semiconductor die to a substrate through an adhesive paste by forming a layer of silicon dioxide on the back surface of the semiconductor die prior to applying the adhesive paste. Contacting the semiconductor die with ozone, in a gas mixture or in a mixture with water provides rapid oxidation of the silicon layer at the back of the semiconductor die to a silicon dioxide layer of at least 10 angstroms thick, which is sufficient to greatly improve bonding to the adhesive. The formation of a silicon dioxide surface layer prior to application of the adhesive is particularly beneficial when combined with rapid, snap curing processes, where the adhesive can be reliably cured by heating the semiconductor die for less than about 1 minute.

Abstract translation: 提供了通过在施加粘合剂糊剂之前通过在半导体管芯的背面上形成二氧化硅层来改善通过粘合剂浆料将半导体管芯粘合到基底上的方法。 将半导体管芯与臭氧，气体混合物或与水的混合物接触将半导体管芯背面的硅层快速氧化成至少10埃的二氧化硅层，这足以大大改善结合 粘合剂。 在施加粘合剂之前形成二氧化硅表面层是特别有利的，当与快速快速固化工艺组合时，其中通过将半导体管芯加热少于约1分钟可以可靠地固化粘合剂。