公开(公告)号：US20180075886A1

公开(公告)日：2018-03-15

申请号：US15695210

申请日：2017-09-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Kiyoshi KATO

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/56 ,  G11C8/08

CPC classification number: G11C7/12 ,  G11C5/148 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4125 ,  G11C11/419 ,  G11C11/565

Abstract: A storage device capable of performing power gating is provided. A memory cell of the storage device includes a bistable circuit, a first transistor, a second transistor, and a backup circuit. The first transistor and the second transistor are electrically connected to a first bit line and a second bit line, respectively. A precharge circuit that precharges the first bit line and the second bit line with different voltages is provided. The backup circuit includes a retention node, an input node, an output node, a third transistor, a fourth transistor, and a capacitor. The third transistor controls electrical continuity between the retention node and the input node. A gate of the fourth transistor and a terminal of the capacitor are electrically connected to the retention node. The input node is electrically connected to one of nodes Q and Qb of the bistable circuit, and the output node is electrically connected to the other of the nodes Q and Qb of the bistable circuit.

公开(公告)号：US20170271337A1

公开(公告)日：2017-09-21

申请号：US15477144

申请日：2017-04-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/105 ,  G11C11/24

CPC classification number: H01L27/105 ,  G11C11/24 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10808 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

Abstract: A semiconductor device including a non-volatile memory cell including a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor is provided. Data is written or rewritten to the memory cell by turning on the writing transistor and supplying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor so that the predetermined amount of charge is held in the node. Further, when a transistor whose threshold voltage is controlled and set to a positive voltage is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US20170236839A1

公开(公告)日：2017-08-17

申请号：US15420628

申请日：2017-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/768 ,  H01L27/105 ,  H01L23/528 ,  H01L23/532 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76825 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US20170194048A1

公开(公告)日：2017-07-06

申请号：US15464395

申请日：2017-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiko ISHIZU ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Wataru UESUGI

IPC: G11C11/419 ,  G11C14/00 ,  G06F3/06

CPC classification number: G11C5/147 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0685 ,  G11C11/419 ,  G11C14/0054

Abstract: Provided is a semiconductor device having a memory cell array, which is capable of existing in three power-gating states depending on a non-access period to the memory cell array. The memory cell array includes a plurality of memory cells which each have an SRAM and a nonvolatile memory portion having a transistor with an oxide semiconductor in a channel region. The three power-gating states includes: a first state in which a power-gating to the memory cell array is performed; a second state in which the power-gating is performed on the memory cell array and peripheral circuits which control the memory cell array; and a third state in which, in addition to the memory cell array and the peripheral circuits, a power supply voltage supplying circuit is subjected to the power gating.

公开(公告)号：US20170154652A1

公开(公告)日：2017-06-01

申请号：US15428207

申请日：2017-02-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: G11C5/10

CPC classification number: G11C5/10 ,  G11C5/06 ,  G11C7/14 ,  G11C11/24 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/419 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5006

Abstract: To provide a small, highly reliable memory device with a large storage capacity. A semiconductor device includes a circuit for retaining data and a circuit for reading data. The circuit for retaining data includes a transistor and a capacitor. The circuit for reading data is configured to supply a potential to the circuit for retaining data and read a potential from the circuit for retaining data. The circuit for retaining data and the circuit for reading data are provided in different layers, so that the semiconductor device with a large storage capacity is manufactured.

公开(公告)号：US20170090231A1

公开(公告)日：2017-03-30

申请号：US15372831

申请日：2016-12-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Toshihiko SAITO

IPC: G02F1/1333 ,  G02F1/1343 ,  H01L27/12 ,  G06F3/044 ,  G06F3/041 ,  G02F1/1368 ,  G02F1/1345

CPC classification number: G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

Abstract: A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

公开(公告)号：US20170077101A1

公开(公告)日：2017-03-16

申请号：US15359873

申请日：2016-11-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki INOUE ,  Kiyoshi KATO ,  Takanori MATSUZAKI ,  Shuhei NAGATSUKA

IPC: H01L27/105 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Abstract translation: 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

公开(公告)号：US20160336055A1

公开(公告)日：2016-11-17

申请号：US15149291

申请日：2016-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO

IPC: G11C11/24 ,  G11C7/06 ,  G11C5/02 ,  G11C11/4091 ,  H01L27/105 ,  H01L29/786 ,  H01L27/12 ,  G11C11/40 ,  H01L23/528

CPC classification number: G11C11/24 ,  G11C5/025 ,  G11C7/062 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4099 ,  G11C11/56 ,  G11C11/565 ,  H01L23/5223 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/7869

Abstract: Provided is a semiconductor device including first to sixth capacitors, first to fourth wirings, first and second sense amplifiers, and a memory cell array over the first and second sense amplifiers. The first wiring is electrically connected to the memory cell array, one electrode of the first capacitor, the third wiring via a source and a drain of a first transistor, the fourth wiring via the fifth capacitor, and the second wiring via the first sense amplifier. The second wiring is electrically connected to one electrode of the second capacitor, the fourth wiring via a source and a drain of a second transistor, and the third wiring via the sixth capacitor. The third wiring is electrically connected to one electrode of the third capacitor, and the fourth wiring via the second sense amplifier. The fourth wiring is electrically connected to one electrode of the fourth capacitor.

Abstract translation: 提供了包括第一至第六电容器，第一至第四布线，第一和第二读出放大器以及第一和第二读出放大器上的存储单元阵列的半导体器件。 第一布线电连接到存储单元阵列，第一电容器的一个电极，经由第一晶体管的源极和漏极的第三布线，经由第五电容器的第四布线，以及经由第一读出放大器的第二布线 。 第二布线经由第二电容器的一个电极，第四布线经由第二晶体管的源极和漏极电连接，并且经由第六电容器电连接到第三布线。 第三布线电连接到第三电容器的一个电极，第四布线经由第二读出放大器电连接。 第四布线电连接到第四电容器的一个电极。

公开(公告)号：US20160293775A1

公开(公告)日：2016-10-06

申请号：US15181621

申请日：2016-06-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Jun KOYAMA

IPC: H01L29/786 ,  G06K19/077 ,  H01L23/66

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

公开(公告)号：US20160226471A1

公开(公告)日：2016-08-04

申请号：US15098391

申请日：2016-04-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Jun KOYAMA

IPC: H03K3/356 ,  H01L27/105 ,  H03K3/037

CPC classification number: H03K3/356104 ,  G11C7/04 ,  G11C14/0063 ,  G11C16/045 ,  G11C2211/4016 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/28202 ,  H01L21/28211 ,  H01L27/105 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/6659 ,  H03K3/0375 ,  H03K3/286 ,  H03K3/356 ,  H03K3/356121 ,  H03K3/356173

Abstract: To provide a novel nonvolatile latch circuit and a semiconductor device using the nonvolatile latch circuit, a nonvolatile latch circuit includes a latch portion having a loop structure where an output of a first element is electrically connected to an input of a second element, and an output of the second element is electrically connected to an input of the first element; and a data holding portion for holding data of the latch portion. In the data holding portion, a transistor using an oxide semiconductor as a semiconductor material for forming a channel formation region is used as a switching element. In addition, an inverter electrically connected to a source electrode or a drain electrode of the transistor is included. With the transistor, data held in the latch portion can be written into a gate capacitor of the inverter or a capacitor which is separately provided.