公开(公告)号：US07948555B2

公开(公告)日：2011-05-24

申请号：US12254354

申请日：2008-10-20

Applicant: Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

Inventor： Yong-Hwan Kwon ,  Un-Byoung Kang ,  Chung-Sun Lee ,  Woon-Seong Kwon ,  Hyung-Sun Jang

IPC: H04N5/225 ,  H04N9/077 ,  H01L31/0232

CPC classification number: H04N5/2254 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2257 ,  H04N2007/145 ,  H01L2924/00

Abstract: A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

Abstract translation: 相机模块包括图像传感器芯片，透镜结构，透明基板，粘合部分和遮光层。 图像传感器芯片包括光接收区域和电路区域。 透镜结构位于图像传感器芯片上并且被配置为允许光进入图像传感器芯片。 透明基板位于图像传感器芯片和透镜结构之间，透明基板允许来自透镜结构的光进入光接收区域。 粘合剂部附着图像传感器芯片和透明基板，并且覆盖电路区域。 遮光层附着到透明基板上以阻挡光线进入电路区域。

公开(公告)号：US20090122178A1

公开(公告)日：2009-05-14

申请号：US12254354

申请日：2008-10-20

Applicant: Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

Inventor： Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Woon-Seong KWON ,  Hyung-Sun JANG

IPC: H04N5/225

CPC classification number: H04N5/2254 ,  H01L27/14618 ,  H01L2924/0002 ,  H04N5/2253 ,  H04N5/2257 ,  H04N2007/145 ,  H01L2924/00

Abstract: A camera module includes an image sensor chip, a lens structure, a transparent substrate, an adhesive portion, and a light blocking layer. The image sensor chip includes a light receiving area and a circuit area. The lens structure is positioned on the image sensor chip and configured to allow light to enter the image sensor chip. The transparent substrate is positioned between the image sensor chip and the lens structure, the transparent substrate allowing light from the lens structure to enter the light receiving area. The adhesive portion attaches the image sensor chip and the transparent substrate, and covers the circuit area. The light blocking layer is attached to the transparent substrate to block light from entering the circuit area.

Abstract translation: 相机模块包括图像传感器芯片，透镜结构，透明基板，粘合部分和遮光层。 图像传感器芯片包括光接收区域和电路区域。 透镜结构位于图像传感器芯片上并且被配置为允许光进入图像传感器芯片。 透明基板位于图像传感器芯片和透镜结构之间，透明基板允许来自透镜结构的光进入光接收区域。 粘合剂部附着图像传感器芯片和透明基板，并且覆盖电路区域。 遮光层附着到透明基板上以阻挡光线进入电路区域。

公开(公告)号：US20080169546A1

公开(公告)日：2008-07-17

申请号：US11952426

申请日：2007-12-07

Applicant: Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

Inventor： Woon-Seong KWON ,  Yong-Hwan KWON ,  Un-Byoung KANG ,  Chung-Sun LEE ,  Hyung-Sun JANG

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L24/48 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/14618 ,  H01L31/0203 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13025 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A stack type semiconductor chip package includes a first wafer mold, a protection substrate, and a second wafer mold that are stacked in a wafer level process. The first wafer mold includes a first chip having first pads and a first mold layer encapsulating the first chip. The protection substrate is placed on the first wafer mold, is mechanically bonded with the first wafer mold using a first adhesive layer, and includes wiring layers facing the first pads. The second wafer mold is placed under the first wafer mold, is mechanically bonded with the first wafer mold using a second adhesive layer, and includes a second chip having second pads, and a second mold layer encapsulating the second chip. First vias electrically connect the wiring layers of the protection substrate with the second pads. Second vias electrically connect the wiring layers of the protection substrate with external connection terminals.

Abstract translation: 堆叠型半导体芯片封装包括在晶片级工艺中堆叠的第一晶片模具，保护基板和第二晶片模具。 第一晶片模具包括具有第一焊盘的第一芯片和封装第一芯片的第一模具层。 保护基板被放置在第一晶片模具上，使用第一粘合剂层与第一晶片模具机械结合，并且包括面向第一焊盘的布线层。 第二晶片模具放置在第一晶片模具下面，使用第二粘合剂层与第一晶片模具机械结合，并且包括具有第二焊盘的第二芯片和封装第二芯片的第二模具层。 第一通孔将保护衬底的布线层与第二衬垫电连接。 第二通孔将保护基板的布线层与外部连接端子电连接。

公开(公告)号：US20070126110A1

公开(公告)日：2007-06-07

申请号：US11670847

申请日：2007-02-02

Applicant: Yong-Hwan KWON ,  Sa-Yoon KANG ,  Chung-Sun LEE ,  Kyoung-Sei CHOI

Inventor： Yong-Hwan KWON ,  Sa-Yoon KANG ,  Chung-Sun LEE ,  Kyoung-Sei CHOI

IPC: H01L23/48

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H05K3/0032 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.

Abstract translation: 为薄膜封装提供具有膜凸块的电路薄膜。 IC芯片通过膜凸块机械连接并电耦合到电路膜，而不是传统的芯片凸块。 在制造方法中，通过激光部分地蚀刻基底膜以产生限定从蚀刻区域相对升高的凸起部分的蚀刻区域。 然后，在基膜上选择性地形成电路图案，部分地在凸起部分上运行。 凸起部分和上覆电路图案构成具有不大于电路膜高度的高度的膜凸块。

公开(公告)号：US20070018324A1

公开(公告)日：2007-01-25

申请号：US11444410

申请日：2006-06-01

Applicant: Yong-hwan Kwon ,  Chung-sun Lee ,  Woon-byung Kang

Inventor： Yong-hwan Kwon ,  Chung-sun Lee ,  Woon-byung Kang

IPC: H01L23/48

CPC classification number: H01L21/6835 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/12 ,  H01L24/96 ,  H01L24/97 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05124 ,  H01L2224/05548 ,  H01L2224/05571 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer-level-chip-scale package and related method of fabrication are disclosed. The wafer-level-chip-scale package comprises a semiconductor substrate comprising an integrated circuit, a conductive ball disposed on the semiconductor substrate and electrically connected to the integrated circuit, and a protective portion formed from an insulating material and disposed on bottom and side surfaces of the semiconductor substrate.

Abstract translation: 公开了一种晶片级芯片级封装及相关的制造方法。 晶片级芯片级封装包括半导体衬底，其包括集成电路，设置在半导体衬底上并与集成电路电连接的导电球，以及由绝缘材料形成并设置在底表面和侧表面上的保护部分 的半导体衬底。

公开(公告)号：US07087987B2

公开(公告)日：2006-08-08

申请号：US10892360

申请日：2004-07-16

Applicant: Ye-Chung Chung ,  Chung-Sun Lee

Inventor： Ye-Chung Chung ,  Chung-Sun Lee

IPC: H01L23/495

CPC classification number: H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/112 ,  H05K3/361 ,  H01L2224/05599

Abstract: A tape circuit substrate and semiconductor chip package using the same. The tape circuit substrate may comprise a base film which may be made of an insulating material and may be formed with via-holes at portions thereof, a first wiring pattern layer which may be formed on a first surface of the base film, and at least one second wiring pattern layer which may be formed on a second surface of the base film and electrically connected to a terminal which may be formed on the first surface through conductive materials, or plugs, filled in the via-holes. The semiconductor chip package may comprise a semiconductor chip which may be electrically bonded to the tape circuit substrate through chip bumps.

Abstract translation: 带状电路基板和使用其的半导体芯片封装。 磁带电路基板可以包括可以由绝缘材料制成并且可以在其部分处形成有通孔的基膜，可以形成在基膜的第一表面上的第一布线图案层，并且至少 一个第二布线图案层可以形成在基膜的第二表面上并且电连接到可以通过填充在通孔中的导电材料或插塞形成在第一表面上的端子。 半导体芯片封装可以包括半导体芯片，其可以通过芯片凸块电连接到磁带电路基板。

公开(公告)号：US20050285277A1

公开(公告)日：2005-12-29

申请号：US11158164

申请日：2005-06-20

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee ,  Kyoung-Sei Choi

IPC: G02F1/1345 ,  H01L21/44 ,  H01L21/56 ,  H01L23/12 ,  H01L23/498 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

CPC classification number: H01L24/32 ,  H01L21/563 ,  H01L23/49811 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/83385 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H05K3/0032 ,  H05K3/323 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit film having film bumps is provided for a film package. An IC chip is mechanically joined and electrically coupled to the circuit film through the film bumps instead of conventional chip bumps. In a fabrication method, a base film is partially etched by a laser to create an etched area that defines raised portion relatively raised from the etched area. Then a circuit pattern is selectively formed on the base film, partly running over the raised portions. The raised portion and the overlying circuit pattern constitute the film bumps having a height not greater than the height of the circuit film.

Abstract translation: 为薄膜封装提供具有膜凸块的电路薄膜。 IC芯片通过膜凸块机械连接并电耦合到电路膜，而不是传统的芯片凸块。 在制造方法中，通过激光部分地蚀刻基底膜以产生限定从蚀刻区域相对升高的凸起部分的蚀刻区域。 然后，在基膜上选择性地形成电路图案，部分地在凸起部分上运行。 凸起部分和上覆电路图案构成具有不大于电路膜高度的高度的膜凸块。

公开(公告)号：US20050205524A1

公开(公告)日：2005-09-22

申请号：US11075639

申请日：2005-03-08

Applicant: Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Kyoung-Sei Choi

Inventor： Chung-Sun Lee ,  Sa-Yoon Kang ,  Yong-Hwan Kwon ,  Kyoung-Sei Choi

IPC: B23K26/36 ,  B23K101/42 ,  C23F1/00 ,  C23F1/18 ,  C23F4/00 ,  C23F4/02 ,  H01L21/60 ,  H05K3/00 ,  H05K3/02 ,  H05K3/06 ,  H05K3/08 ,  H05K3/46

CPC classification number: C23F1/18 ,  C23F1/02 ,  C23F4/02 ,  H05K3/027 ,  H05K3/06 ,  H05K2203/0369 ,  H05K2203/0783 ,  H05K2203/1121 ,  H05K2203/1476

Abstract: A method of manufacturing a tape wiring substrate, by which the production cost can be reduced by a simplified manufacturing process. A fine wiring pattern having fine pitches can be formed. The method of manufacturing a tape wiring substrate includes preparing a base film, forming a metal layer on the base film, and processing the metal layer into a wiring pattern using a laser. In addition, the metal layer is partially removed using the laser, and a wiring pattern is formed by a subsequent wet etching.

Abstract translation: 制造带状布线基板的方法，通过简化的制造工艺可以降低生产成本。 可以形成具有细间距的精细布线图案。 制造带状布线基板的方法包括制备基膜，在基膜上形成金属层，并使用激光将金属层加工成布线图案。 此外，使用激光部分地去除金属层，并且通过随后的湿蚀刻形成布线图案。

公开(公告)号：US20050017343A1

公开(公告)日：2005-01-27

申请号：US10898445

申请日：2004-07-22

Applicant: Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

Inventor： Yong-Hwan Kwon ,  Sa-Yoon Kang ,  Chung-Sun Lee

IPC: H01L21/44 ,  H01L21/60 ,  H01L23/31 ,  H01L23/485

CPC classification number: H01L24/11 ,  H01L23/3114 ,  H01L24/12 ,  H01L24/16 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Provided are a method of forming a bump whose upper surface is substantially flat and whose area can be enlarged in a uniform pad pitch to simplify mounting a liquid crystal display drive IC (LDI) and a semiconductor chip and a mount structure using the method to minimize a pad area inside the chip. Thus, the pad area on an edge of a conventional chip is minimized and the bump is formed in a substantially flat location inside the chip and an electrical connection between the pad and the bump is performed by a redistribution metal line.

Abstract translation: 提供了一种形成凸起的方法，该凸块的上表面基本上是平的，并且其面积可以以均匀的垫间距扩大，以简化安装液晶显示驱动IC（LDI）和半导体芯片以及使用该方法的安装结构 芯片内部的焊盘区域。 因此，传统芯片的边缘上的焊盘区域被最小化，并且凸块形成在芯片内部的基本上平坦的位置，并且焊盘和凸块之间的电连接由再分布金属线执行。

公开(公告)号：US08604615B2

公开(公告)日：2013-12-10

申请号：US13174813

申请日：2011-07-01

Applicant: Chung-Sun Lee ,  Jung-Hwan Kim ,  Tae-Hong Min ,  Hyun-Jung Song ,  Sun-Pil Youn

Inventor： Chung-Sun Lee ,  Jung-Hwan Kim ,  Tae-Hong Min ,  Hyun-Jung Song ,  Sun-Pil Youn

IPC: H01L23/48 ,  H01L21/82 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05552 ,  H01L2224/81 ,  H01L2224/83

Abstract: A stack of semiconductor chips, a semiconductor device, and a method of manufacturing are disclosed. The stack of semiconductor chips may comprise a first chip of the stack, a second chip of the stack over the first chip, conductive bumps, a homogeneous integral underfill material, and a molding material. The conductive bumps may extend between an upper surface of the first chip and a lower surface of the second chip. The homogeneous integral underfill material may be interposed between the first chip and the second chip, encapsulate the conductive bumps, and extend along sidewalls of the second chip. The homogeneous integral underfill material may have an upper surface extending in a direction parallel to an upper surface of the second chip and located adjacent the upper surface of the second chip. The molding material may be on outer side surfaces of the homogeneous integral underfill material above the upper surface of the first chip, wherein, in view of a first cross sectional profile, the molding material is separated from sidewalls of the second chip by the homogeneous integral underfill material such that the molding material does not contact sidewalls of the second chip.

Abstract translation: 公开了一叠半导体芯片，半导体器件和制造方法。 堆叠的半导体芯片可以包括堆叠的第一芯片，第一芯片上的堆叠的第二芯片，导电凸块，均匀的整体底部填充材料和模制材料。 导电凸块可以在第一芯片的上表面和第二芯片的下表面之间延伸。 均匀整体的底部填充材料可以插入在第一芯片和第二芯片之间，封装导电凸块，并且沿着第二芯片的侧壁延伸。 均匀整体的底部填充材料可以具有在与第二芯片的上表面平行的方向上延伸并且位于第二芯片的上表面附近的上表面。 模制材料可以在第一芯片的上表面之上的均匀整体底部填充材料的外侧表面上，其中，从第一横截面轮廓的角度来看，模制材料通过均匀的积分与第二芯片的侧壁分离 底部填充材料，使得模制材料不接触第二芯片的侧壁。