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    METHOD OF MAKING THROUGH WAFER VIAS
    12.
    发明申请
    METHOD OF MAKING THROUGH WAFER VIAS 有权
    通过WAVER VIAS制作的方法

    公开(公告)号：US20100035430A1

    公开(公告)日：2010-02-11

    申请号：US12188230

    申请日：2008-08-08

    Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

    IPC: H01L21/768

    CPC classification number: H01L21/76898

    Abstract: A method of making a through wafer via. The method includes: forming a trench in a semiconductor substrate, the trench open to a top surface of the substrate; forming a polysilicon layer on sidewalls and a bottom of the trench; oxidizing the polysilicon layer to convert the polysilicon layer to a silicon oxide layer on the sidewalls and bottom of the trench, the silicon oxide layer not filling the trench; filling remaining space in the trench with an electrical conductor; and thinning the substrate from a bottom surface of the substrate and removing the silicon oxide layer from the bottom of the trench. The method may further include forming a metal layer on the silicon oxide layer before filling the trench.

    Abstract translation: 制造通过晶片通孔的方法。 该方法包括：在半导体衬底中形成沟槽，沟槽通向衬底的顶表面; 在沟槽的侧壁和底部上形成多晶硅层; 氧化多晶硅层以将多晶硅层转变成沟槽的侧壁和底部上的氧化硅层，氧化硅层不填充沟槽; 用电导体填充沟槽中的剩余空间; 以及从衬底的底表面使衬底细化并从沟槽的底部去除氧化硅层。 该方法还可以包括在填充沟槽之前在氧化硅层上形成金属层。

    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME
    13.
    发明申请
    LOW RESISTANCE AND INDUCTANCE BACKSIDE THROUGH VIAS AND METHODS OF FABRICATING SAME 有权
    通过VIAS的低电阻和电感及其制造方法

    公开(公告)号：US20090184423A1

    公开(公告)日：2009-07-23

    申请号：US12410728

    申请日：2009-03-25

    Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

    IPC: H01L23/48 ,  H01L21/30

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

    Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

    Through substrate annular via including plug filler
    14.
    发明授权
    Through substrate annular via including plug filler 有权
    通过基底环形通孔，包括塞子填料

    公开(公告)号：US07898063B2

    公开(公告)日：2011-03-01

    申请号：US12032642

    申请日：2008-02-16

    Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

    IPC: H01L23/48

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

    Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

    Wafer-to-wafer alignments
    16.
    发明授权
    Wafer-to-wafer alignments 失效
    晶圆对晶圆对准

    公开(公告)号：US07474104B2

    公开(公告)日：2009-01-06

    申请号：US11557668

    申请日：2006-11-08

    Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffee ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffee ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

    IPC: G01R27/26 ,  H01L23/544

    CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

    Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

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