公开(公告)号：US20110156269A1

公开(公告)日：2011-06-30

申请号：US12834115

申请日：2010-07-12

Applicant: Jong Hyun NAM ,  Ki Young KIM ,  Jin Ho BAE

Inventor： Jong Hyun NAM ,  Ki Young KIM ,  Jin Ho BAE

IPC: H01L23/48

CPC classification number: H01L23/49833 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48464 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor chip having a first region defined at a center portion of a first surface of the semiconductor chip, and having second and third regions defined on both sides of the first region, respectively. Bonding pads are disposed in the first region and a substrate having a substrate body is disposed in the second region of the semiconductor chip. The substrate includes an extension portion projecting away from the semiconductor chip. The substrate also includes circuit patterns disposed on the substrate body having a first ends placed adjacent to the bonding pads and second ends placed on the extension portion. Connection members electrically connect the first ends of the circuit patterns and the bonding pads.

Abstract translation: 半导体封装包括半导体芯片，其具有限定在半导体芯片的第一表面的中心部分处的第一区域，并且具有分别限定在第一区域两侧的第二和第三区域。 接合焊盘设置在第一区域中，并且具有基板主体的基板设置在半导体芯片的第二区域中。 基板包括远离半导体芯片突出的延伸部分。 衬底还包括布置在衬底主体上的电路图案，其具有邻近接合焊盘放置的第一端和放置在延伸部分上的第二端。 连接构件电连接电路图案的第一端和接合垫。

公开(公告)号：US20090152708A1

公开(公告)日：2009-06-18

申请号：US12049661

申请日：2008-03-17

Applicant: Woong Sun LEE ,  Qwan Ho CHUNG ,  Il Hwan CHO ,  Sang Joon LIM ,  Jong Woo YOO ,  Jin Ho BAE ,  Seung Hyun LEE

Inventor： Woong Sun LEE ,  Qwan Ho CHUNG ,  Il Hwan CHO ,  Sang Joon LIM ,  Jong Woo YOO ,  Jin Ho BAE ,  Seung Hyun LEE

IPC: H01L23/498

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83007 ,  H01L2224/83138 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Abstract translation: 用于半导体封装的衬底包括具有第一表面和与第一表面相对的第二表面的衬底本体。 在第一表面的边缘附近形成连接垫。 形成具有导电通孔和第一，第二和第三线部分的信号线。 第一线部分形成在第一表面上并且连接到穿过基板主体的连接焊盘和导电通孔。 第二线部分形成在第一表面上并连接到导电通孔。 第三线部分形成在第二表面上并连接到导电通孔。 第二和第三线部分形成为具有基本相同的长度。 半导体封装利用上述基板高速处理数据。

公开(公告)号：US20060016467A1

公开(公告)日：2006-01-26

申请号：US11038833

申请日：2005-01-18

Applicant: Jin-Ho Bae

Inventor： Jin-Ho Bae

IPC: E04H15/28

CPC classification number: E04H15/48 ,  E04H15/28

Abstract: The present invention provides a bell folding tent typically comprised of awnings and framework consisted of poles, wherein the framework includes a top static rib-hub built upon the top end of a main stick setting on the center vertically, and hanged on with radial ribs, which is combined of several segments and connectors connecting said adjacent segments together, a low sliding rib-hub put on the main stick in sliding fitting for hanging up one ends of braces, the another ends of said braces pivoted on the first segments of the ribs respectively; an elastic piece is set upon the main stick between said low sliding rib-hub with the top end and the bottom end of the main stick with the low end. Due to the saved restoring energy of the stretched elastic piece, as opening the tent, the low sliding rib-hub is pulled down continuously and kept the inner ends of the braces having a downward pulling force so that the outer ends of braces are kept a strutting force upward to support all ribs to brace the tent without any falling down, and not need to attach any holding device, and the service life is increased greatly.

Abstract translation: 本发明提供一种钟形折叠帐篷，通常由遮阳篷和由杆组成的框架组成，其中框架包括一个顶部的静态肋毂，该顶部静态肋毂设置在垂直于中心的中心的主体的顶端上， 其组合有将连接所述相邻节段的几个部分和连接器组合在一起，将滑动配件中放置在主棒上的低滑动肋毂用于悬挂支架的一端，所述支架的另一端在肋条的第一段上枢转 分别; 弹性件被放置在所述低滑动肋毂之间的主杆上，并且具有低端的主杆的顶端和底端。 由于拉伸的弹性片的恢复能量被保存，因为打开帐篷，所以低滑动肋毂被连续地拉下并保持支架的内端具有向下的拉力，使得支架的外端保持 向上支撑支撑所有肋骨以支撑帐篷而不会掉落，并且不需要附接任何夹持装置，并且使用寿命大大增加。

公开(公告)号：US08796834B2

公开(公告)日：2014-08-05

申请号：US13118714

申请日：2011-05-31

Applicant: Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

Inventor： Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

IPC: H01L23/522

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/82 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.

Abstract translation: 堆叠包括具有第一表面和第二表面的芯层，并且包括第一电路布线; 设置在所述芯层的第二表面上的第一半导体器件; 形成在所述芯层的第二表面上以覆盖所述第一半导体器件的第一树脂层; 形成在第一树脂层上并与第一半导体器件电连接的第二电路布线; 设置在包括第二电路布线的第一树脂层上并与第二电路布线电连接的第二半导体装置; 第二树脂层，形成在第二电路布线和第一树脂层上以覆盖第二半导体器件; 以及形成为穿过第一树脂层和芯层并且电连接第一电路布线和第二电路布线的多个通孔图案。

公开(公告)号：US08441116B2

公开(公告)日：2013-05-14

申请号：US13465274

申请日：2012-05-07

Applicant: Woong Sun Lee ,  Qwan Ho Chung ,  Il Hwan Cho ,  Sang Joon Lim ,  Jong Woo Yoo ,  Jin Ho Bae ,  Seung Hyun Lee

Inventor： Woong Sun Lee ,  Qwan Ho Chung ,  Il Hwan Cho ,  Sang Joon Lim ,  Jong Woo Yoo ,  Jin Ho Bae ,  Seung Hyun Lee

IPC: H01L23/48

CPC classification number: H01L23/5384 ,  H01L23/5386 ,  H01L24/29 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83007 ,  H01L2224/83138 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The substrate for a semiconductor package includes a substrate body having a first surface and a second surface opposite to the first surface. Connection pads are formed near an edge of the first surface. Signal lines having conductive vias and first, second, and third line parts are formed. The first line parts are formed on the first surface and are connected to the connection pads and the conductive vias, which pass through the substrate body. The second line parts are formed on the first surface and connect to the conductive vias. The third line parts are formed on the second surface and connect to the conductive vias. The second and third line parts are formed to have substantially the same length. The semiconductor package utilizes the above substrate for processing data at a high speed.

Abstract translation: 用于半导体封装的衬底包括具有第一表面和与第一表面相对的第二表面的衬底本体。 在第一表面的边缘附近形成连接垫。 形成具有导电通孔和第一，第二和第三线部分的信号线。 第一线部分形成在第一表面上并且连接到穿过基板主体的连接焊盘和导电通孔。 第二线部分形成在第一表面上并连接到导电通孔。 第三线部分形成在第二表面上并连接到导电通孔。 第二和第三线部分形成为具有基本相同的长度。 半导体封装利用上述基板高速处理数据。

公开(公告)号：US20120205797A1

公开(公告)日：2012-08-16

申请号：US13339123

申请日：2011-12-28

Applicant: Jin Ho BAE ,  Myung Gun PARK

Inventor： Jin Ho BAE ,  Myung Gun PARK

IPC: H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L23/5256 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13575 ,  H01L2224/13666 ,  H01L2224/13681 ,  H01L2224/13684 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06565 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/19102 ,  H01L2924/19107 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/049 ,  H01L2924/01014 ,  H01L2924/01007 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bump includes a metal pillar formed over a structural body; and a diffusion barrier member formed to cover at least a portion of a side surface of the metal pillar.

Abstract translation: 凸块包括形成在结构体上的金属柱; 以及形成为覆盖金属柱的侧表面的至少一部分的扩散阻挡构件。

公开(公告)号：US20120007236A1

公开(公告)日：2012-01-12

申请号：US13168107

申请日：2011-06-24

Applicant: Jin Ho BAE

Inventor： Jin Ho BAE

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L23/498 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83194 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device includes a semiconductor substrate having an upper surface, a lower surface, a first side and a second side, wherein the lower surface has a slope so that the first side is thicker than the second side, and a circuit pattern including a bonding pad on the upper surface of the semiconductor substrate.

Abstract translation: 半导体器件包括具有上表面，下表面，第一侧和第二侧的半导体衬底，其中下表面具有斜面，使得第一侧比第二侧厚;以及电路图案，包括接合 衬垫在半导体衬底的上表面上。

公开(公告)号：US20110193213A1

公开(公告)日：2011-08-11

申请号：US12980772

申请日：2010-12-29

Applicant: Jin Ho BAE ,  Ki Young KIM ,  Jong Hyun NAM

Inventor： Jin Ho BAE ,  Ki Young KIM ,  Jong Hyun NAM

IPC: H01L23/48

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L24/09 ,  H01L24/16 ,  H01L24/18 ,  H01L24/20 ,  H01L24/29 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/17104 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/078 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A stacked semiconductor chip includes a main substrate supporting a semiconductor chip module, wherein the semiconductor module comprises at least two sub semiconductor chip modules each having a sub substrate in which a first semiconductor chip is embedded and at least two second semiconductor chips are stacked on the sub substrate.

Abstract translation: 叠层半导体芯片包括支撑半导体芯片模块的主衬底，其中半导体模块包括至少两个次半导体芯片模块，每个子半导体芯片模块具有嵌入第一半导体芯片的子衬底和至少两个第二半导体芯片堆叠在其上 副底物。

公开(公告)号：US08829689B2

公开(公告)日：2014-09-09

申请号：US12980533

申请日：2010-12-29

Applicant: Ki Young Kim ,  Sung Ho Hyun ,  Myung Gun Park ,  Jin Ho Bae

Inventor： Ki Young Kim ,  Sung Ho Hyun ,  Myung Gun Park ,  Jin Ho Bae

IPC: H01L23/053 ,  H01L23/14 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H05K7/20 ,  H05K7/00 ,  H05K3/22 ,  H01L21/66 ,  H01L25/065 ,  H01L23/00 ,  H05K3/34

CPC classification number: H01L24/81 ,  H01L22/14 ,  H01L22/20 ,  H01L24/16 ,  H01L24/48 ,  H01L24/799 ,  H01L24/98 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/225 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/176 ,  H01L2924/00 ,  H01L2224/45099

Abstract: A module substrate may include a substrate body on which a plurality of chip mounting regions having connection pads are defined. Repair structures may be respectively formed, or placed, in the chip mounting regions. Each repair structure includes conductive layer patterns formed over the connection pads in each chip mounting region, an insulation layer pattern formed over the substrate body in each chip mounting region in such a way as to expose the conductive layer patterns, plastic conductive members formed between the connection pads and the conductive layer patterns, and a plastic insulation member formed between the substrate body and the insulation layer pattern in each chip mounting region.

Abstract translation: 模块基板可以包括其上限定了具有连接焊盘的多个芯片安装区域的基板主体。 修补结构可以分别形成或放置在芯片安装区域中。 每个修复结构包括形成在每个芯片安装区域中的连接焊盘上的导电层图案，在每个芯片安装区域中形成在衬底主体上的绝缘层图案，以暴露导电层图案，形成在导体层图案之间的塑料导电构件 连接焊盘和导电层图案，以及在每个芯片安装区域中形成在基板主体和绝缘层图案之间的塑料绝缘构件。

公开(公告)号：US08823183B2

公开(公告)日：2014-09-02

申请号：US12981329

申请日：2010-12-29

Applicant: Ki Young Kim ,  Qwan Ho Chung ,  Sung Ho Hyun ,  Myung Gun Park ,  Jin Ho Bae

Inventor： Ki Young Kim ,  Qwan Ho Chung ,  Sung Ho Hyun ,  Myung Gun Park ,  Jin Ho Bae

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/13 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02377 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/13006 ,  H01L2224/13008 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13193 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14155 ,  H01L2224/14156 ,  H01L2224/16059 ,  H01L2224/1607 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/01083 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere.

Abstract translation: 半导体封装的凸块包括：形成在半导体芯片上并具有至少两个焊盘部分的第一凸块和连接焊盘部分并且具有小于焊盘部分的线宽的连接部分; 以及形成在所述第一凸块上并且以半球形状突出在所述第一凸块的所述陆部上的第二凸块。