公开(公告)号：US20110156230A1

公开(公告)日：2011-06-30

申请号：US12651080

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H01L25/065 ,  H01L21/77 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06589

Abstract: A multi-stack semiconductor dice assembly has enhanced board-level reliability and integrated electrical functionalities over a common package foot-print. The multi-stack semiconductor dice assembly includes a bottom die having a stepped upper surface. The stepped upper surface includes a base region and a stepped region, which is raised relative to the base region. The base region includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls. An upper die is stacked above the bottom die. The upper die includes a plurality of attachment structures that are sized and shaped to receive electrically conductive balls and are arranged to align with the attachment structures of the bottom die. Electrically conductive balls are attached to the attachment structures of the bottom die and the attachment structures of the upper die.

Abstract translation: 多堆叠半导体晶片组件在普通封装脚印上增强了板级可靠性和集成电气功能。 多层半导体晶片组件包括具有阶梯状上表面的底模。 台阶状上表面包括基部区域和相对于基底区域升高的阶梯状区域。 基部区域包括多个附接结构，其尺寸和形状被容纳以接纳导电球。 上模具堆叠在底模上方。 上模具包括多个附接结构，其尺寸和形状适于容纳导电球，并且被布置成与底模的附接结构对准。 导电球连接到底模的附接结构和上模的附接结构。

公开(公告)号：US07361995B2

公开(公告)日：2008-04-22

申请号：US10543301

申请日：2004-02-03

Applicant: Kim Yong Goh ,  Rahul Kapoor ,  Anthony Yi-Sheng Sun ,  Desmond Yok Rue Chong ,  Lan H. Hoang

Inventor： Kim Yong Goh ,  Rahul Kapoor ,  Anthony Yi-Sheng Sun ,  Desmond Yok Rue Chong ,  Lan H. Hoang

IPC: H01L29/40

CPC classification number: H01L23/4334 ,  H01L23/04 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/1659 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0401 ,  H01L2924/00

Abstract: A thermally enhanced ball grid array package is disclosed. The package includes a base layer element and a flip chip die mounted on the base layer element. The die has a first surface electrically coupled to the base layer element, a second surface opposite to the first surface, and lateral sides. A molding compound encapsulates the base layer element and the lateral sides of the die. A surface is formed of the second surface of the die and an upper surface of the molding compound. A material is disposed on the surface, and a heat spreader is mounted on the material.

Abstract translation: 公开了一种热增强球栅阵列封装。 封装包括安装在基底层元件上的基底元件和倒装芯片裸片。 模具具有电耦合到基层元件的第一表面，与第一表面相对的第二表面和横向侧面。 模制化合物封装基底层元件和模具的侧面。 表面由模具的第二表面和模塑料的上表面形成。 材料设置在表面上，散热器安装在材料上。

公开(公告)号：US08018036B2

公开(公告)日：2011-09-13

申请号：US11602098

申请日：2006-11-20

Applicant: Kim-yong Goh ,  Tong-yan Tee

Inventor： Kim-yong Goh ,  Tong-yan Tee

IPC: H01L23/24

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract translation: 一种超薄四边形扁平无铅（QFN）半导体芯片封装，其具有引线框架，该引线框架具有由顶部和底部表面的凹部形成的引线端子和形成在顶部或底部表面上的基本上对准的接触区域。 模具电连接到多个引线端子，并且模制化合物将引线框封装在一起，以形成超薄QFN封装。 因此，基本对准的接触区域暴露在封装的顶表面和底表面上。 本公开还提供了一种超薄光学四方扁平无引线（OQFN）半导体芯片封装，包括至少两个QFN半导体芯片封装的堆叠半导体模块，以及用于制造超薄四面体扁平无铅 QFN）半导体封装。

公开(公告)号：US08884422B2

公开(公告)日：2014-11-11

申请号：US12651365

申请日：2009-12-31

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L23/04 ,  H01L29/40 ,  H01L25/10 ,  H01L23/498 ,  H01L21/56 ,  H01L25/16 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L21/565 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/19 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2924/00

Abstract: A flip-chip fan-out wafer level package for package-on-package applications includes a semiconductor die with solder bumps on an upper surface in a flip chip configuration. The die is inverted, with an upper surface facing an upper side of a redistribution layer, with the solder bumps in electrical contact with respective chip contact pads of the redistribution layer. The redistribution layer includes conductive traces that place each of the solder bumps in electrical contact with one or both of one of a plurality of upper redistribution contact pads and one of a plurality of lower redistribution contact pads. Each of the plurality of upper redistribution contact pads has an upper solder ball in electrical contact therewith. The die and the upper solder balls are at least partially encapsulated in a layer of mold compound positioned on the upper surface of the redistribution layer, and whose lateral dimensions are defined by the lateral dimensions of the redistribution layer. The layer of mold compound has a back-ground surface at which a portion of each of the upper solder balls is exposed, for electrical contact with an upper package. Each of the lower redistribution contact pads has a lower solder ball a coupled thereto.

Abstract translation: 用于封装封装应用的倒装芯片扇出晶片级封装包括在倒装芯片配置的上表面上具有焊料凸块的半导体管芯。 模具倒置，上表面面向再分布层的上侧，焊料凸块与再分布层的相应芯片接触焊盘电接触。 再分配层包括导电迹线，其将每个焊料凸点与多个上再分布接触焊盘和多个下再分布接触焊盘之一中的一个或两者电接触。 多个上再分配接触垫中的每一个具有与其接触的上焊球。 模具和上焊球至少部分地封装在位于再分配层的上表面上的模具化合物层中，并且其横向尺寸由再分布层的横向尺寸限定。 模具化合物层具有背面表面，每个上焊球的一部分暴露在其中，用于与上封装电接触。 每个下再分布接触垫具有与其耦合的较低焊球。

公开(公告)号：US08796826B2

公开(公告)日：2014-08-05

申请号：US13335467

申请日：2011-12-22

Applicant: Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

Inventor： Xueren Zhang ,  Kim-Yong Goh ,  Wingshenq Wong

IPC: H01L23/495 ,  H01L21/44 ,  B23K31/02 ,  B23K37/04

CPC classification number: H01L24/78 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/78 ,  H01L2224/85001 ,  H01L2924/14 ,  H01L2924/3025 ,  Y10T29/53265 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

Abstract: A device and method for minimizing the forces that may compromise a lead frame mount to a support structure in an integrated circuit die package during various packaging method steps. When a window clamp is used to provide pressure during a lead frame bonding step or during a wire bonding step during packaging, the vertical force applied by the window clamp may be transferred in lateral direction by the physical contour of the top plate of the support structure. By changing the physical contour of the top plate of the support structure, such as by disposing a specific kind of contoured protrusion, one may minimize or eliminate the lateral forces that act against achieving a solid bond of the lead frame to the support structure. Further, during wire bonding, the same minimization or elimination of lateral forces lead to improved wire bonding.

Abstract translation: 一种用于在各种包装方法步骤期间最小化可能危及引线框安装件到集成电路管芯封装中的支撑结构的力的装置和方法。 当使用窗夹来在包装期间在引线框接合步骤期间或在引线接合步骤期间提供压力时，由窗夹具施加的垂直力可以通过支撑结构的顶板的物理轮廓在横向方向上传递 。 通过改变支撑结构的顶板的物理轮廓，例如通过设置特定类型的轮廓突起，可以最小化或消除作用于实现引线框架与支撑结构的牢固结合的侧向力。 此外，在引线接合期间，相同的最小化或消除侧向力导致改善的引线接合。

公开(公告)号：US08772943B2

公开(公告)日：2014-07-08

申请号：US13313397

申请日：2011-12-07

Applicant: Xueren Zhang ,  Kim-Yong Goh

Inventor： Xueren Zhang ,  Kim-Yong Goh

IPC: H01L29/72

CPC classification number: H01L24/05 ,  H01L21/563 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05092 ,  H01L2224/05124 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05681 ,  H01L2224/06051 ,  H01L2224/061 ,  H01L2224/13027 ,  H01L2224/13147 ,  H01L2224/14104 ,  H01L2224/14131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An integrated circuit die has a dielectric layer positioned over all the contact pads on the integrated circuit die. Openings are provided in the dielectric layer over each of the contact pads of the integrated circuit die in order to permit electrical coupling to be made between the integrated circuit and circuit boards outside of the die. For those contact pads located in the central region of the die, the opening in the dielectric layer is in a central region of the contact pad. For those contact pads located in a peripheral region of the die, spaced adjacent the perimeter die, the opening in the dielectric layer is offset from the center of the contact pad and is positioned closer to the central region of the die than the center of the contact pad is to the central region of the die.

Abstract translation: 集成电路管芯具有位于集成电路管芯上的所有接触焊盘上的电介质层。 在集成电路管芯的每个接触焊盘上的介电层中设置开口，以便允许在集成电路和管芯外部的电路板之间进行电耦合。 对于位于管芯的中心区域的接触焊盘，电介质层中的开口位于接触焊盘的中心区域。 对于那些位于模具周边区域的接触垫，邻近周边模具间隔开，电介质层中的开口偏离接触焊盘的中心，并且位于比芯片中心更靠近模具的中心区域 接触垫是到模具的中心区域。

公开(公告)号：US20120028397A1

公开(公告)日：2012-02-02

申请号：US13196641

申请日：2011-08-02

Applicant: Kim-yong Goh ,  Tong-yan Tee

Inventor： Kim-yong Goh ,  Tong-yan Tee

IPC: H01L21/56

CPC classification number: H01L23/3107 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An ultra-thin Quad Flat No-Lead (QFN) semiconductor chip package having a leadframe with lead terminals formed by recesses from both the top and bottom surfaces and substantially aligned contact areas formed on either the top or bottom surfaces. A die is electrically connected to the plurality of lead terminals and a molding compound encapsulates the leadframe and die together so as to form the ultra-thin QFN package. Accordingly, the substantially aligned contact areas are exposed on both the top and bottom surfaces of the package. The present disclosure also provides an ultra-thin Optical Quad Flat No-Lead (OQFN) semiconductor chip package, a stacked semiconductor module comprising at least two QFN semiconductor chip packages, and a method for manufacturing an ultra-thin Quad Flat No-Lead (QFN) semiconductor packages.

Abstract translation: 一种超薄四边形扁平无铅（QFN）半导体芯片封装，其具有引线框架，该引线框架具有由顶部和底部表面的凹部形成的引线端子，以及形成在顶部或底部表面上的基本上对准的接触区域。 模具电连接到多个引线端子，并且模制化合物将引线框封装在一起，以形成超薄QFN封装。 因此，基本对准的接触区域暴露在封装的顶表面和底表面上。 本公开还提供了一种超薄光学四方扁平无引线（OQFN）半导体芯片封装，包括至少两个QFN半导体芯片封装的堆叠半导体模块，以及用于制造超薄四面体扁平无铅 QFN）半导体封装。

公开(公告)号：US20110157853A1

公开(公告)日：2011-06-30

申请号：US12651295

申请日：2009-12-31

Applicant: Kim-Yong Goh

Inventor： Kim-Yong Goh

IPC: H05K7/00 ,  H05K1/00 ,  H01R43/00

CPC classification number: H01L23/3128 ,  H01L21/563 ,  H01L23/293 ,  H01L24/05 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/80 ,  H01L2224/03334 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05571 ,  H01L2224/08238 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/221 ,  H01L2224/80357 ,  H01L2224/804 ,  H01L2224/80815 ,  H01L2224/814 ,  H01L2924/0002 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/3025 ,  Y10T29/49117 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.

Abstract translation: 包含电子封装中的球栅阵列的焊料元件的聚合物层。 聚合物层通过将球栅阵列的元件包围在粘合到封装结构的刚性聚合物层中来加强焊球组分界面处的焊料接合。 通过球栅阵列施加到封装的应力通过聚合物层传递到封装结构，绕过焊点并改善机电电路的可靠性。 在制造聚合物层的方法的一个实施方案中，与封装结构上的外部焊盘接合的焊料元素浸没在聚合物层的流体形式中。 流体形式被固化，然后去除所得聚合物层的一部分，以使焊料元件可接近以将封装安装到印刷电路板或其它外部电路。

公开(公告)号：US20100148363A1

公开(公告)日：2010-06-17

申请号：US12336273

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/498 ,  H01L21/60

CPC classification number: H01L23/3128 ,  H01L21/561 ,  H01L23/49816 ,  H01L24/28 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A ball grid array (BGA) package includes a substrate layer having first and second sides. A semiconductor chip is attached to the first side of the substrate layer by a dielectric adhesive layer. A plurality of solder balls are attached to the second side of the substrate layer. The solder balls may be set out by rows and columns. A plurality of wires electrically connect the semiconductor chip to the solder balls. A layer of encapsulating compound is deposited over the semiconductor chip. A step cavity of a selected depth and shape is formed in the layer of encapsulating compound at or near the edge or periphery of the layer of encapsulating compound. The step cavity is separated from the solder balls by the substrate layer but spans over a plurality of selected solder balls.

Abstract translation: 球栅阵列（BGA）封装包括具有第一侧和第二侧的衬底层。 半导体芯片通过介电粘合剂层附接到基板层的第一侧。 多个焊球附着在基板层的第二面上。 焊球可以由行和列排列。 多个电线将半导体芯片电连接到焊球。 一层封装化合物沉积在半导体芯片上。 在密封化合物层的边缘或周边处或附近，在封装化合物层中形成所选择的深度和形状的台阶腔。 阶跃腔通过衬底层与焊球分离，但跨越多个选定的焊球。

公开(公告)号：US20100148347A1

公开(公告)日：2010-06-17

申请号：US12336422

申请日：2008-12-16

Applicant: Kim-Yong Goh ,  Jing-En Luan

Inventor： Kim-Yong Goh ,  Jing-En Luan

IPC: H01L23/043 ,  H01L23/52 ,  H01L21/02

CPC classification number: H01L23/367 ,  H01L23/04 ,  H01L23/3114 ,  H01L23/552 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/16152 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A chip scale package (CSP) device includes a CSP having a semiconductor die electrically coupled to a plurality of solder balls. A can having an inside top surface and one or more side walls defines a chamber. The CSP is housed in the chamber and is attached to the inside top surface of the can. A printed circuit board is attached to the solder balls and to the one or more side walls to provide support to the CSP and to the can. The CSP may be a Wafer-Level CSP. The can may be built from a metallic substance or from a non-metallic substance. The can provides stress relief to the CSP during a drop test and during a thermal cycle test.

Abstract translation: 芯片级封装（CSP）器件包括具有电耦合到多个焊球的半导体管芯的CSP。 具有内顶表面和一个或多个侧壁的罐体限定了一个室。 CSP容纳在腔室中，并连接到罐的内部顶部表面。 印刷电路板附接到焊球和一个或多个侧壁以提供对CSP和罐的支撑。 CSP可能是晶片级CSP。 罐可以由金属物质或非金属物质制成。 在跌落测试期间和热循环测试期间，罐可以为CSP提供应力消除。