中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.017 seconds)

    Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner
    11.
    发明申请
    Dielectric Gap Fill With Oxide Selectively Deposited Over Silicon Liner 审中-公开
    介质间隙填充选择性沉积在硅衬里上的氧化物

    公开(公告)号：US20070087522A1

    公开(公告)日：2007-04-19

    申请号：US11565726

    申请日：2006-12-01

    Applicant: Srinivas Nemani ,  Shankar Venkataraman

    Inventor： Srinivas Nemani ,  Shankar Venkataraman

    IPC: H01L21/76

    CPC classification number: H01L21/76229

    Abstract: A thin layer of silicon is deposited within a high aspect ratio feature to provide a template for selective deposition of oxide therein. In accordance with one embodiment, amorphous silicon is deposited within a shallow trench feature overlying an oxide liner grown therein. After exposure to sputtering to remove the amorphous silicon from outside of the trench, oxide is selectively deposited over the amorphous silicon to fill the trench from the bottom up without voids, thereby creating a shallow trench isolation (STI) structure. Deposition of the amorphous silicon or other silicon containing layers allows the selective oxide deposition step to be integrated with a thermally-grown oxide trench liner.

    Abstract translation: 在高纵横比特征中沉积薄层硅以提供用于在其中选择性沉积氧化物的模板。 根据一个实施例，在覆盖其中生长的氧化物衬垫的浅沟槽特征中沉积非晶硅。 在暴露于溅射之后从沟槽外部去除非晶硅时，氧化物被选择性地沉积在非晶硅之上，以从底部向上填充沟槽而无空隙，从而产生浅沟槽隔离（STI）结构。 非晶硅或其它含硅层的沉积允许选择性氧化物沉积步骤与热生长的氧化物沟槽衬里整合。

    Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions
    12.
    发明授权
    Methods for depositing premetal dielectric layer at sub-atmospheric and high temperature conditions 失效
    在低于大气压和高温条件下沉积金属前介质层的方法

    公开(公告)号：US5963840A

    公开(公告)日：1999-10-05

    申请号：US748960

    申请日：1996-11-13

    Applicant: Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

    Inventor： Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

    IPC: C23C14/00 ,  C23C16/30 ,  C23C16/40 ,  C23C16/511 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/44

    CPC classification number: H01L21/31625 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02362

    Abstract: The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

    Abstract translation: 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

    PATTERN FORMATION AND TRANSFER DIRECTLY ON SILICON BASED FILMS
    14.
    发明申请
    PATTERN FORMATION AND TRANSFER DIRECTLY ON SILICON BASED FILMS 审中-公开
    图形形成和直接传播基于硅的薄膜

    公开(公告)号：US20150132959A1

    公开(公告)日：2015-05-14

    申请号：US14075971

    申请日：2013-11-08

    Applicant: Leonard TEDESCHI ,  Srinivas NEMANI

    Inventor： Leonard TEDESCHI ,  Srinivas NEMANI

    IPC: H01L21/308 ,  H01L21/67 ,  H01L21/02

    CPC classification number: H01L21/67213 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/0337 ,  H01L21/311 ,  H01L21/31144

    Abstract: Embodiments involve patterned mask formation. In one embodiment, a method involves depositing a CVD film over a semiconductor wafer; exposing the CVD film to e-beam or UV radiation, forming a pattern in the CVD film; and etching the pattern in the CVD film, forming features in areas not exposed to the e-beam or UV radiation. In one embodiment, a method involves depositing a CVD film over a semiconductor wafer; depositing a thin photo-sensitive CVD hardmask film over the CVD film; exposing the thin photo-sensitive CVD hardmask film to e-beam or UV radiation, forming a pattern in the thin photo-sensitive CVD hardmask film; etching the pattern in the thin photo-sensitive CVD hardmask film; etching the pattern into the CVD film through the patterned thin photo-sensitive CVD hardmask film; and removing the patterned thin photo-sensitive CVD hardmask film.

    Abstract translation: 实施例涉及图案化掩模形成。 在一个实施例中，一种方法包括在半导体晶片上沉积CVD膜; 将CVD膜暴露于电子束或UV辐射，在CVD膜中形成图案; 并蚀刻CVD膜中的图案，在不暴露于电子束或UV辐射的区域中形成特征。 在一个实施例中，一种方法包括在半导体晶片上沉积CVD膜; 在CVD膜上沉积薄的光敏CVD硬掩模膜; 将薄的光敏CVD硬掩模膜暴露于电子束或UV辐射，在薄的光敏CVD硬掩模膜中形成图案; 蚀刻薄光敏CVD硬掩模膜中的图案; 通过图案化的薄光敏CVD硬掩模膜将图案蚀刻到CVD膜中; 并去除图案化的光敏CVD硬掩模膜。

    Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers
    16.
    发明授权
    Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers 失效
    双频等离子体增强化学气相沉积碳化硅层

    公开(公告)号：US06465366B1

    公开(公告)日：2002-10-15

    申请号：US09660268

    申请日：2000-09-12

    Applicant: Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

    Inventor： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

    IPC: H01L2131

    CPC classification number: H01L21/76829 ,  C23C16/325 ,  C23C16/505 ,  H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/7681

    Abstract: A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

    Abstract translation: 公开了一种用于形成用于集成电路制造的碳化硅层的方法。 通过在电场的存在下使包含硅源，碳源和惰性气体的气体混合物反应来形成碳化硅层。 使用混频射频（RF）功率产生电场。 碳化硅层与集成电路制造工艺兼容。 在一个集成电路制造工艺中，碳化硅层用作用于制造集成电路结构的硬掩模，例如镶嵌结构。 在另一个集成电路制造工艺中，碳化硅层用作用于DUV光刻的抗反射涂层（ARC）。

    DIELECTRIC DEPOSITION AND ETCH BACK PROCESSES FOR BOTTOM UP GAPFILL
    20.
    发明申请
    DIELECTRIC DEPOSITION AND ETCH BACK PROCESSES FOR BOTTOM UP GAPFILL 有权
    用于底盖的介电沉积和回填工艺

    公开(公告)号：US20070298585A1

    公开(公告)日：2007-12-27

    申请号：US11765944

    申请日：2007-06-20

    Applicant: Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh

    Inventor： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh

    IPC: H01L21/76

    CPC classification number: H01L21/76229

    Abstract: Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

    Abstract translation: 描述了减少电介质层中的膜破裂的方法。 所述方法可以包括以下步骤：在衬底上沉积第一电介质膜并通过对膜进行蚀刻来去除第一电介质膜的顶部。 所述方法还可以包括在蚀刻的第一膜上沉积第二电介质膜，以及去除第二电介质膜的顶部。 此外，所述方法可以包括退火第一和第二介电膜以形成电介质层，其中从第一和第二电介质膜去除顶部部分降低了介电层中的应力水平。

Patent Agency Ranking