公开(公告)号：US08587132B2

公开(公告)日：2013-11-19

申请号：US13665634

申请日：2012-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。

公开(公告)号：US09431371B2

公开(公告)日：2016-08-30

申请号：US14701388

申请日：2015-04-30

Applicant: BROADCOM CORPORATION

Inventor： Sampath K. Karikalan ,  Sam Ziqun Zhao ,  Kevin Kunzhong Hu ,  Rezaur Rahman Khan ,  Pieter Vorenkamp ,  Xiangdong Chen

IPC: H01L25/00 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/538 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/82 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/152 ,  H01L2924/1532 ,  H01L2924/30105 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).

公开(公告)号：US20150340308A1

公开(公告)日：2015-11-26

申请号：US14323759

申请日：2014-07-03

Applicant: Broadcom Corporation

Inventor： Edward LAW ,  Sam Ziqun Zhao ,  Kunzhong Hu ,  Rezaur Rahman Khan

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05672 ,  H01L2224/06135 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1041 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00014

Abstract: A reconstituted semiconductor package and a method of making a reconstituted semiconductor package are described. An array of die-attach substrates is formed onto a carrier. A semiconductor device is mounted onto a first surface of each of the die-attach substrates. An interposer substrate is mounted over each of the semiconductor devices. The interposer substrates are electrically connected to the first surface of the respective die-attach substrates. A molding compound is filled in open spaces within and between the interposer substrates mounted to their respective die-attach substrates to form an array of reconstituted semiconductor packages. Electrical connections are mounted to a second surface of the die-attach substrates. The array of reconstituted semiconductor packages is singulated through the molding compound between each of the die-attach substrates and respective mounted interposer substrates.

Abstract translation: 描述了重构的半导体封装和制造重构的半导体封装的方法。 芯片附着基板的阵列形成在载体上。 半导体器件安装在每个裸片附着衬底的第一表面上。 插入器基板安装在每个半导体器件上。 插入器基板电连接到各个管芯附着基板的第一表面。 将模塑料填充在安装到它们各自的管芯附着衬底上的插入器衬底之内和之间的开放空间中，以形成重构的半导体封装的阵列。 电连接被安装到管芯附接衬底的第二表面。 重新组装的半导体封装的阵列通过模具化合物在每个裸片附着衬底和相应的安装的插入器衬底之间分割。

公开(公告)号：US09070627B2

公开(公告)日：2015-06-30

申请号：US14031000

申请日：2013-09-18

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/105 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/29007 ,  H01L2224/29012 ,  H01L2224/29014 ,  H01L2224/29015 ,  H01L2224/29035 ,  H01L2224/29036 ,  H01L2224/29078 ,  H01L2224/2919 ,  H01L2224/3012 ,  H01L2224/30131 ,  H01L2224/30141 ,  H01L2224/30179 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/831 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/9221 ,  H01L2224/92242 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An integrated circuit (IC) package includes an IC die having a first surface and a second surface opposite of the first surface. The IC package includes first contact members coupled to the second surface of the IC die. The IC package includes a bottom substrate having a first surface and a second surface opposite of the first surface, where the first surface of the bottom substrate is coupled to the second surface of the IC die via the first contact members. The IC package includes an interposer substrate coupled to the first surface of the IC die via an adhesive material, where the adhesive material is disposed on at least a surface of the interposer substrate. The IC package includes second contact members coupled along a periphery of the interposer substrate, where the interposer substrate is coupled to the first surface of the bottom substrate via the second contact members.

Abstract translation: 集成电路（IC）封装包括具有第一表面和与第一表面相对的第二表面的IC管芯。 IC封装包括耦合到IC管芯的第二表面的第一接触构件。 IC封装包括具有第一表面和与第一表面相对的第二表面的底部衬底，其中底部衬底的第一表面经由第一接触构件联接到IC管芯的第二表面。 IC封装包括通过粘合剂材料耦合到IC管芯的第一表面的插入器基板，其中粘合材料设置在中介层基板的至少一个表面上。 IC封装包括沿着插入器衬底的周边耦合的第二接触构件，其中插入器衬底经由第二接触构件联接到底部衬底的第一表面。

公开(公告)号：US20150179610A1

公开(公告)日：2015-06-25

申请号：US14147237

申请日：2014-01-03

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/528 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L25/0655 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/48 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014

Abstract: Systems, apparatuses, and methods provided for semiconductor devices and integrated circuit (IC) packages that include compliant dielectric layers. In a through silicon via interposer or substrate, a compliant dielectric material may be added to a surface of silicon material body to form a compliant dielectric layer. The compliant dielectric layer provides a thermal buffer and a stress buffer for a resulting IC package. The compliant dielectric material may be selected such that the coefficient of thermal expansion of the compliant dielectric material approximately matches the coefficient of thermal expansion of the circuit board on which the IC package is mounted. The compliant dielectric material may be selected such that it has a deformability that is greater than the silicon material body. Multiple sub-layers of compliant dielectric material may be used.

Abstract translation: 为半导体器件和集成电路（IC）封装提供的系统，装置和方法，其包括兼容的电介质层。 在通过硅通孔插入器或衬底中，柔性介电材料可以被添加到硅材料体的表面以形成柔顺的介电层。 柔性电介质层为所得IC封装提供热缓冲器和应力缓冲器。 柔性介电材料可以被选择成使得柔性介电材料的热膨胀系数近似匹配安装有IC封装的电路板的热膨胀系数。 可以选择兼容的介电材料，使得其具有大于硅材料体的可变形性。 可以使用多个顺应介电材料的子层。

公开(公告)号：US09046576B2

公开(公告)日：2015-06-02

申请号：US13944430

申请日：2013-07-17

Applicant: Broadcom Corporation

Inventor： Arya Reza Behzad ,  Ahmadreza Rofougaran ,  Sam Ziqun Zhao ,  Jesus Alfonso Castaneda ,  Michael Boers

IPC: G01R31/00 ,  G01R31/319 ,  G01R31/302 ,  G01R31/311 ,  H01L23/544 ,  G01R31/28

CPC classification number: G01R31/319 ,  G01R31/2834 ,  G01R31/3025 ,  G01R31/311 ,  H01L23/544 ,  H01L2223/54433 ,  H01L2924/0002 ,  Y10T29/49121 ,  H01L2924/00

Abstract: Methods and apparatus are disclosed to simultaneously, wirelessly test semiconductor components formed on a semiconductor wafer. The semiconductor components transmit respective outcomes of a self-contained testing operation to wireless automatic test equipment via a common communication channel. Multiple receiving antennas observe the outcomes from multiple directions in three dimensional space. The wireless automatic test equipment determines whether one or more of the semiconductor components operate as expected and, optionally, may use properties of the three dimensional space to determine a location of one or more of the semiconductor components. The wireless testing equipment may additionally determine performance of the semiconductor components by detecting infrared energy emitted, transmitted, and/or reflected by the semiconductor wafer before, during, and/or after a self-contained testing operation.

Abstract translation: 公开了同时无线地测试形成在半导体晶片上的半导体元件的方法和装置。 半导体部件通过公共通信信道将各自的测试结果传送到无线自动测试设备。 多个接收天线在三维空间中观察多个方向的结果。 无线自动测试设备确定一个或多个半导体组件是否按预期运行，并且可选地，可以使用三维空间的属性来确定一个或多个半导体组件的位置。 无线测试设备还可以通过检测在独立测试操作之前，期间和/或之后由半导体晶片发射，传输和/或反射的红外能量来确定半导体组件的性能。

公开(公告)号：US08823144B2

公开(公告)日：2014-09-02

申请号：US14052466

申请日：2013-10-11

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L29/40 ,  H01L23/02 ,  H01L23/48 ,  H01L23/52

CPC classification number: H01L23/481 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract translation: 公开了一种界面衬底，其包括具有贯通半导体通孔的插入件。 进一步围绕插入件构建上部和下部有机衬底。 所公开的接口衬底能够持续使用低成本且广泛部署的用于半导体封装的有机衬底，同时提供若干优点。 将有机基底分离成上下基板能够实现制造设备的成本有效匹配。 通过在一个有机衬底中设置一个开口，一个或多个半导体管芯可以附着到与插入器的通孔半导体连接的暴露的互连焊盘上，使得能够使用具有高密度微型阵列的倒装芯片和模具 具有不同的凸起间距。 通过在上部有机衬底中提供开口，还可以提供具有优化的高度的封装封装结构。

公开(公告)号：US20140035162A1

公开(公告)日：2014-02-06

申请号：US14051817

申请日：2013-10-11

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman Khan ,  Sam Ziqun Zhao

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An interface substrate is disclosed which includes an interposer having through-semiconductor vias. An upper and a lower organic substrate are further built around the interposer. The disclosed interface substrate enables the continued use of low cost and widely deployed organic substrates for semiconductor packages while providing several advantages. The separation of the organic substrate into upper and lower substrates enables the cost effective matching of fabrication equipment. By providing an opening in one of the organic substrates, one or more semiconductor dies may be attached to exposed interconnect pads coupled to through-semiconductor vias of the interposer, enabling the use of flip chips with high-density microbump arrays and the accommodation of dies with varied bump pitches. By providing the opening specifically in the upper organic substrate, a package-on-package structure with optimized height may also be provided.

Abstract translation: 公开了一种界面衬底，其包括具有贯通半导体通孔的插入件。 进一步围绕插入件构建上部和下部有机衬底。 所公开的接口衬底能够持续使用低成本且广泛部署的用于半导体封装的有机衬底，同时提供若干优点。 将有机基底分离成上下基板能够实现制造设备的成本有效匹配。 通过在一个有机衬底中设置一个开口，一个或多个半导体管芯可以附着到与插入器的通孔半导体连接的暴露的互连焊盘上，使得能够使用具有高密度微型阵列的倒装芯片和模具 具有不同的凸起间距。 通过在上部有机衬底中提供开口，还可以提供具有优化的高度的封装封装结构。

公开(公告)号：US20130295723A1

公开(公告)日：2013-11-07

申请号：US13929240

申请日：2013-06-27

Applicant: Broadcom Corporation

Inventor： Rezaur Rahman KHAN ,  Sam Ziqun Zhao

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit (IC) package is provided. The method includes mounting a fast plurality of contact members on a surface of a package member, and coupling a second plurality of contact members located on a first surface of an interposer substrate to corresponding ones of the first plurality of contact members. The interposer substrate is configured such that a circuit member mounted to a second surface of the interposer substrate is electrically coupled to the first plurality of contact members.

Abstract translation: 提供一种制造集成电路（IC）封装的方法。 该方法包括将快速多个接触构件安装在封装构件的表面上，以及将位于中介层基板的第一表面上的第二多个接触构件与第一多个接触构件中的相应接触构件连接。 插入器基板被配置为使得安装到插入器基板的第二表面的电路构件电耦合到第一多个接触构件。

公开(公告)号：US20130214426A1

公开(公告)日：2013-08-22

申请号：US13665634

申请日：2012-10-31

Applicant: Broadcom Corporation

Inventor： Sam Ziqun Zhao ,  Rezaur Rahman Khan

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/4857 ,  H01L23/14 ,  H01L23/145 ,  H01L23/147 ,  H01L23/49506 ,  H01L23/49575 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/97 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/30183 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/1515 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The present application discloses various implementations of a semiconductor package including an organic substrate and one or more interposers having through-semiconductor vias (TSVs). Such a semiconductor package may include a contiguous organic substrate having a lower substrate segment including first and second pluralities of lower interconnect pads, the second plurality of lower interconnect pads being disposed in an opening of the lower substrate segment. The contiguous organic substrate may also include an upper substrate segment having an upper width and including first and second pluralities of upper interconnect pads. In addition, the semiconductor package may include at least one interposer having TSVs for electrically connecting the first and second pluralities of lower interconnect pads to the first and second pluralities of upper interconnect pads. The interposer has an interposer width less than the upper width of the upper substrate segment.

Abstract translation: 本申请公开了包括有机衬底和具有贯通半导体通孔（TSV）的一个或多个中介层的半导体封装的各种实施方式。 这种半导体封装可以包括具有包括第一和第二多个下部互连焊盘的下部衬底区段的连续有机衬底，第二多个下部互连焊盘设置在下部衬底段的开口中。 连续的有机衬底还可以包括具有上部宽度并包括第一和第二多个上部互连焊盘的上部衬底区段。 此外，半导体封装可以包括具有TSV的至少一个插入器，用于将第一和第二多个下部互连焊盘电连接到第一和第二多个上部互连焊盘。 插入器具有小于上基板段的上宽度的插入器宽度。