公开(公告)号：US20080274583A1

公开(公告)日：2008-11-06

申请号：US11690181

申请日：2007-03-23

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Kenneth Jay Stein ,  Timothy Dooling Sullivan ,  Cornelia Kang-I Tsang ,  Ping-Chuan Wang ,  Bucknell C. Webb

IPC: H01L21/00

CPC classification number: H01L23/481 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A through-wafer via structure and method for forming the same. The through-wafer via structure includes a wafer having an opening and a top wafer surface. The top wafer surface defines a first reference direction perpendicular to the top wafer surface. The through-wafer via structure further includes a through-wafer via in the opening. The through-wafer via has a shape of a rectangular plate. A height of the through-wafer via in the first reference direction essentially equals a thickness of the wafer in the first reference direction. A length of the through-wafer via in a second reference direction is at least ten times greater than a width of the through-wafer via in a third reference direction. The first, second, and third reference directions are perpendicular to each other.

Abstract translation: 一种晶片通孔结构及其形成方法。 贯通晶片通孔结构包括具有开口和顶部晶片表面的晶片。 顶部晶片表面限定垂直于顶部晶片表面的第一参考方向。 贯通晶片通孔结构还包括在开口中的通晶片通孔。 贯通晶片通孔具有矩形板的形状。 贯通晶片通孔在第一参考方向上的高度基本上等于晶片在第一参考方向上的厚度。 贯穿晶片通孔在第二参考方向上的长度比通过晶片通孔在第三参考方向上的宽度大至少十倍。 第一，第二和第三参考方向彼此垂直。

公开(公告)号：US06642080B1

公开(公告)日：2003-11-04

申请号：US09691546

申请日：2000-10-18

Applicant: Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

Inventor： Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Abstract translation: 公开了各种特性的片上芯片互连，例如直径，高度和/或组成的变化。 在接合平面上的第一芯片上芯片互连具有第一特性（例如，第一高度），并且在同一接合平面上的第二芯片上芯片互连具有第二特性（例如，第二高度大于 第一高度）。 片上芯片互连的第一和第二特性允许片上芯片连接到其他封装，基板或不同级别和/或组成的芯片。

公开(公告)号：US06507115B2

公开(公告)日：2003-01-14

申请号：US09736584

申请日：2000-12-14

Applicant: Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

Inventor： Harm Peter Hofstee ,  Robert Kevin Montoye ,  Edmund Juris Sprogis

IPC: H01L2348

CPC classification number: H01L23/4334 ,  H01L23/3677 ,  H01L23/49816 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05599 ,  H01L2224/16145 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A multi-chip module is disclosed in which a first die connects to a second set of die via a set of C4 connections within a single package. Low resistivity signal posts are provided within the lateral separation between adjacent die in the second set of die. These signal posts are connectable to externally supplied power signals. The power signals provided to the signals posts are routed to circuits within the second set of die over relatively short metallization interconnects. The signal posts may be connected to thermally conductive via elements and the package may include heat spreaders on upper and lower package surfaces. The first die may comprise a DRAM while the second set of die comprise portions of a general purpose microprocessor. The power signals provided to the second set of die may be connected to a capacitor terminal in the first die to provide power signal decoupling.

公开(公告)号：US5977640A

公开(公告)日：1999-11-02

申请号：US105419

申请日：1998-06-26

Applicant: Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

Inventor： Claude Louis Bertin ,  Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

IPC: H01L25/18 ,  H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L24/73 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331

Abstract: The advantages of the invention are realized by a chip-on-chip module having at least two fully functional chips, electrically connected together, and a chip-on-chip component connection/interconnection for electrically connecting the fully functional chips to external circuitry.

Abstract translation: 本发明的优点通过具有至少两个完全功能的芯片，电连接在一起的片上芯片模块和用于将全功能芯片电连接到外部电路的片上芯片组件连接/互连来实现。

公开(公告)号：US07898063B2

公开(公告)日：2011-03-01

申请号：US12032642

申请日：2008-02-16

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US20090085202A1

公开(公告)日：2009-04-02

申请号：US11862609

申请日：2007-09-27

Applicant: Bing Dang ,  Mario J. Interrante ,  John Ulrich Knickerbocker ,  Edmund Juris Sprogis ,  Son K. Tran

Inventor： Bing Dang ,  Mario J. Interrante ,  John Ulrich Knickerbocker ,  Edmund Juris Sprogis ,  Son K. Tran

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H01L21/4853 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2203/016 ,  H01L2924/00

Abstract: Methods of assembling an integrated circuit are provided. An interposer supported by an integrated handler is solder bumped onto one or more bond pads on a substrate. The integrated handler is removed from the interposer. A side of the interposer opposite that of the substrate is solder bumped to one or more bond pads on a chip.

Abstract translation: 提供组装集成电路的方法。 由集成处理器支持的插入器焊接在衬底上的一个或多个接合焊盘上。 集成处理程序从插入器中删除。 插入器的与衬底相反的一侧是焊接到芯片上的一个或多个接合焊盘。

公开(公告)号：US07474104B2

公开(公告)日：2009-01-06

申请号：US11557668

申请日：2006-11-08

Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffee ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffee ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: G01R27/26 ,  H01L23/544

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US07348210B2

公开(公告)日：2008-03-25

申请号：US10908084

申请日：2005-04-27

Applicant: Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

Inventor： Timothy H. Daubenspeck ,  Jeffrey Peter Gambino ,  Christopher David Muzzy ,  Wolfgang Sauter ,  Edmund Juris Sprogis

IPC: H01L21/00

CPC classification number: H01L23/556 ,  H01L24/02 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A structure and a method for forming the same. The method includes (a) providing a structure which includes (i) a dielectric layer, (ii) an electrically conducting bond pad on and in direct physical contact with the dielectric layer top surface, (iii) a first passivation layer on the dielectric layer top surface and on the electrically conducting bond pad, wherein the first passivation layer comprises a first hole directly above the electrically conducting bond pad, and (iv) an electrically conducting solder bump filling the first hole and electrically coupled to the electrically conducting bond pad; and (b) forming a second passivation layer on the first passivation layer, wherein second passivation layer is in direct physical contact with the electrically conducting solder bump, and wherein the electrically conducting solder bump is exposed to a surrounding ambient immediately after said forming the second passivation layer is performed.

Abstract translation: 一种结构及其形成方法。 该方法包括（a）提供一种结构，其包括（i）电介质层，（ii）与电介质层顶表面直接物理接触的导电接合焊盘，（iii）介电层上的第一钝化层 其中所述第一钝化层包括位于所述导电接合焊盘正上方的第一孔，以及（iv）填充所述第一孔并电耦合到所述导电接合焊盘的导电焊料凸块; 以及（b）在所述第一钝化层上形成第二钝化层，其中第二钝化层与所述导电焊料凸块直接物理接触，并且其中所述导电焊料凸点在所述第二钝化层形成所述第二钝化层之后立即暴露于周围环境 执行钝化层。

公开(公告)号：US07276787B2

公开(公告)日：2007-10-02

申请号：US10729254

申请日：2003-12-05

Applicant: Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

Inventor： Daniel Charles Edelstein ,  Paul Stephen Andry ,  Leena Paivikki Buchwalter ,  Jon Alfred Casey ,  Sherif A. Goma ,  Raymond R. Horton ,  Gareth Geoffrey Hougham ,  Michael Wayne Lane ,  Xiao Hu Liu ,  Chirag Suryakant Patel ,  Edmund Juris Sprogis ,  Michelle Leigh Steen ,  Brian Richard Sundlof ,  Cornelia K. Tsang ,  George Frederick Walker

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/4763 ,  H01L29/40 ,  H01L23/52

CPC classification number: H01L23/49883 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.

Abstract translation: 一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于 或者与衬底的密切匹配。 导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯， 具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

公开(公告)号：US06225699B1

公开(公告)日：2001-05-01

申请号：US09105477

申请日：1998-06-26

Applicant: Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

Inventor： Thomas George Ference ,  Wayne John Howell ,  Edmund Juris Sprogis

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/29099 ,  H01L2924/00

Abstract: Chip-on-chip interconnections of varied characteristics, such as varied diameters, heights and/or composition, are disclosed. A first chip-on-chip interconnection on a joining plane has a first characteristic (e.g., a first height) and a second chip-on-chip interconnection on the same joining plane has a second characteristic (e.g., a second height greater than the first height). The first and second characteristics of the chip-on-chip interconnections allow for chip-on-chip connections to other packages, substrates or chips of different levels and/or compositions.

Abstract translation: 公开了各种特性的片上芯片互连，例如直径，高度和/或组成的变化。 在接合平面上的第一芯片上芯片互连具有第一特性（例如，第一高度），并且在同一接合平面上的第二芯片上芯片互连具有第二特性（例如，第二高度大于 第一高度）。 片上芯片互连的第一和第二特性允许片上芯片连接到其他封装，基板或不同级别和/或组成的芯片。