公开(公告)号：US20100284140A1

公开(公告)日：2010-11-11

申请号：US12839094

申请日：2010-07-19

申请人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

发明人： David J. Corisis ,  Lee Choon Kuan ,  Chin Hui Chong

IPC分类号： H05K1/11 ,  G06F1/16

CPC分类号： H05K1/115 ,  G01R31/026 ,  G06F1/16 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0221 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/0296 ,  H05K1/18 ,  H05K3/42 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/09809 ,  Y10T29/49165 ,  H01L2924/00

摘要： Electronic devices include a substrate with first and second pairs of conductive traces extending in or on the substrate. A first conductive interconnecting member extends through a hole in the substrate and communicates electrically with a first trace of each of the first and second pairs, while a second conductive interconnecting member extends through the hole and communicates electrically with the second trace of each of the first and second pairs. The first and second interconnecting members are separated from one another by a distance substantially equal to a distance separating the conductive traces in each pair. Electronic device assemblies include a transmitting device configured to transmit a differential signal through a conductive structure to a receiving device. The conductive structure includes first and second pair of conductive traces with first and second interconnecting members providing electrical communication therebetween.

摘要翻译： 电子器件包括具有在衬底中或衬底上延伸的第一和第二对导电迹线的衬底。 第一导电互连构件延伸穿过衬底中的孔并且与第一和第二对中的每一个的第一迹线电连通，而第二导电互连构件延伸穿过孔并与第一导电互连构件中的每一个的第二迹线电连通 和第二对。 第一和第二互连构件彼此间隔开距离，该距离基本上等于分隔每对导电迹线的距离。 电子设备组件包括被配置为通过导电结构将差分信号传输到接收设备的发送设备。 导电结构包括第一和第二对导电迹线，其中第一和第二互连构件之间提供电连通。

公开(公告)号：US20100173454A1

公开(公告)日：2010-07-08

申请号：US12726130

申请日：2010-03-17

申请人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

发明人： Chin Hui Chong ,  Choon Kuan Lee ,  David J. Corisis

IPC分类号： H01L21/60

CPC分类号： H01L23/4951 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4952 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49171 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49146 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.

摘要翻译： 公开了具有引线框架的微电子封装，包括配置用于堆叠管芯封装的引线框架，以及相关系统和方法。 根据一个实施例的系统包括具有电耦合到引线框架键合位置的第一封装焊接位置的支撑构件。 微电子管芯可以由支撑构件承载并电耦合到第一封装的粘结位置。 引线框架可以附接到引线框架结合位置，以便在裸片定位在引线框架和支撑构件之间的同时延伸到微电子模具附近。 引线框架可以包括背离第一封装焊接位置的第二封装焊接位置。 密封剂可以至少部分地围绕引线框架和微电子管芯，其中第一和第二封装结合位置可从密封剂外部接近。

公开(公告)号：US07745920B2

公开(公告)日：2010-06-29

申请号：US12136717

申请日：2008-06-10

申请人： Choon Kuan Lee ,  Chin Hui Chong ,  David J. Corisis

发明人： Choon Kuan Lee ,  Chin Hui Chong ,  David J. Corisis

IPC分类号： H01L23/02 ,  H01L23/34 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/29 ,  H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/29005 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

摘要翻译： 本文公开了用于制造封装的微电子器件的封装的微电子器件和方法。 在一个实施例中，封装的微电子器件可以包括支撑构件，附接到支撑构件的第一模具和以堆叠构造附接到第一模具的第二模具。 该装置还可以包括在第一和第二管芯之间的附接特征。 附着特征可以由介电粘合剂材料构成。 附接特征包括（a）覆盖第二管芯的至少近似全部后侧的单个整体结构，以及（b）电耦合到第一管芯和第二管芯的内部主动特征的多个互连结构 。

公开(公告)号：US20100117212A1

公开(公告)日：2010-05-13

申请号：US12689624

申请日：2010-01-19

申请人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

发明人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC分类号： H01L25/065 ,  H01L21/98 ,  H01L23/52

CPC分类号： H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

摘要翻译： 本文公开了堆叠的微电子器件和用于制造这种器件的方法。 在一个实施例中，堆叠的微电子器件组件可以包括包括第一插入器衬底的第一已知的良好封装的微电子器件。 第一管芯和第一穿通管互连件电耦合到第一插入器衬底。 第一壳体至少部分地封装第一装置，使得每个第一互连件的一部分在第一壳体的顶部可接近。 第二已知的良好封装的微电子器件以堆叠配置耦合到第一器件。 第二器件可以包括具有多个第二插入器焊盘的第二插入器衬底和与第二插入器衬底电耦合的第二管芯。 第一互连的暴露部分电耦合到对应的第二插入器焊盘。

公开(公告)号：US20100109149A1

公开(公告)日：2010-05-06

申请号：US12683104

申请日：2010-01-06

申请人： David J. Corisis ,  Tongbi Jiang

发明人： David J. Corisis ,  Tongbi Jiang

IPC分类号： H01L23/498

CPC分类号： H01L23/49827 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

摘要翻译： 公开了一种器件，其包括：芯片，其包括集成电路和耦合到管芯的插入器，所述插入器具有比所述管芯小的占地面积。 公开了一种方法，其包括将插入件可操作地耦合到包括集成电路的管芯，所述插入器具有比所述管芯更小的占地面积，以及用底部填充材料填充所述插入件与所述管芯之间的空间。

公开(公告)号：US07671459B2

公开(公告)日：2010-03-02

申请号：US11414864

申请日：2006-05-01

申请人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

发明人： David J. Corisis ,  Chin Hui Chong ,  Choon Kuan Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/053 ,  H01L21/56 ,  H01L21/561 ,  H01L22/10 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/49805 ,  H01L23/49861 ,  H01L23/5389 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/105 ,  H01L25/117 ,  H01L2224/05554 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06503 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1627 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Stacked microelectronic devices and methods for manufacturing such devices are disclosed herein. In one embodiment, a stacked microelectronic device assembly can include a first known good packaged microelectronic device including a first interposer substrate. A first die and a first through-casing interconnects are electrically coupled to the first interposer substrate. A first casing at least partially encapsulates the first device such that a portion of each first interconnect is accessible at a top portion of the first casing. A second known good packaged microelectronic device is coupled to the first device in a stacked configuration. The second device can include a second interposer substrate having a plurality of second interposer pads and a second die electrically coupled to the second interposer substrate. The exposed portions of the first interconnects are electrically coupled to corresponding second interposer pads.

摘要翻译： 本文公开了堆叠的微电子器件和用于制造这种器件的方法。 在一个实施例中，堆叠的微电子器件组件可以包括包括第一插入器衬底的第一已知的良好封装的微电子器件。 第一管芯和第一穿通管互连件电耦合到第一插入器衬底。 第一壳体至少部分地封装第一装置，使得每个第一互连件的一部分在第一壳体的顶部可接近。 第二已知的良好封装的微电子器件以堆叠配置耦合到第一器件。 第二器件可以包括具有多个第二插入器焊盘的第二插入器衬底和与第二插入器衬底电耦合的第二管芯。 第一互连的暴露部分电耦合到对应的第二插入器焊盘。

公开(公告)号：US07659151B2

公开(公告)日：2010-02-09

申请号：US11734497

申请日：2007-04-12

申请人： David J. Corisis ,  Tongbi Jiang

发明人： David J. Corisis ,  Tongbi Jiang

IPC分类号： H01L21/50 ,  H01L23/29

CPC分类号： H01L23/49827 ,  H01L21/563 ,  H01L23/3114 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A device is disclosed which includes a die comprising an integrated circuit and an interposer that is coupled to the die, the interposer having a smaller footprint than that of the die. A method is disclosed which includes operatively coupling an interposer to a die comprising an integrated circuit, the interposer having a smaller footprint than that of the die, and filling a space between the interposer and the die with an underfill material.

摘要翻译： 公开了一种器件，其包括：芯片，其包括集成电路和耦合到管芯的插入器，所述插入器具有比所述管芯小的占地面积。 公开了一种方法，其包括将插入件可操作地耦合到包括集成电路的管芯，所述插入器具有比所述管芯更小的占地面积，以及用底部填充材料填充所述插入件与所述管芯之间的空间。

公开(公告)号：US07511364B2

公开(公告)日：2009-03-31

申请号：US10931775

申请日：2004-08-31

申请人： David J. Corisis

发明人： David J. Corisis

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/85424 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device assembly includes a semiconductor device and a lead frame having lead fingers for connection to the semiconductor device. The lead frame may include floating no connect (NC) lead fingers with inner portions of the floating NC lead fingers electrically isolated from the semiconductor device and the associated outer portion of the floating NC lead fingers. Floating NC lead fingers may separate lead fingers prone to causing induction noise from lead fingers subject to induction effects. The floating NC lead fingers may also allow the semiconductor device to be securely adhered to the lead fingers with no air pockets therebetween. A method of forming a semiconductor device assembly is also provided.

摘要翻译： 半导体器件组件包括半导体器件和具有用于连接到半导体器件的引线指引的引线框架。 引线框架可以包括浮动的无连接（NC）引线指，其中浮动NC引线指的内部部分与半导体器件电气隔离，并且浮动NC引线的相关外部部分。 浮动的NC引线指可以分离导线手指，容易引起来自引线感应电感的感应噪声。 浮动的NC引线指也可允许半导体器件牢固地粘附到引线指，其间没有气泡。 还提供了一种形成半导体器件组件的方法。

公开(公告)号：US20080254571A1

公开(公告)日：2008-10-16

申请号：US11786610

申请日：2007-04-12

申请人： David J. Corisis ,  Matt Schwab

发明人： David J. Corisis ,  Matt Schwab

IPC分类号： H01L21/00 ,  H01L23/00

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00012

摘要： There is provided a semiconductor device assembly with an interposer and method of manufacturing the same. More specifically, in one embodiment, there is provided a semiconductor device assembly comprising a semiconductor substrate, at least one semiconductor die attached to the semiconductor substrate, an interposer disposed on the semiconductor die, and a controller attached to the interposer. There is also provided a method of manufacturing comprising forming a first subassembly by coupling a substrate and a semiconductor die, and forming second subassembly by attaching a controller to an interposer, and coupling the first subassembly to the second subassembly.

摘要翻译： 提供了一种具有插入件的半导体器件组件及其制造方法。 更具体地，在一个实施例中，提供了一种半导体器件组件，包括半导体衬底，附接到半导体衬底的至少一个半导体管芯，设置在半导体管芯上的插入器和附接到插入器的控制器。 还提供了一种制造方法，包括通过耦合衬底和半导体管芯来形成第一子组件，以及通过将控制器附接到插入件来形成第二子组件，以及将第一子组件耦合到第二子组件。

公开(公告)号：US07423336B2

公开(公告)日：2008-09-09

申请号：US10118366

申请日：2002-04-08

申请人： David J. Corisis ,  Jerry M. Brooks ,  Matt E. Schwab ,  Tracy V. Reynolds

发明人： David J. Corisis ,  Jerry M. Brooks ,  Matt E. Schwab ,  Tracy V. Reynolds

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.

摘要翻译： 一种用于半导体器件的重新路由元件，其包括承载导电通孔，导电元件和接触焊盘的电介质膜。 导电通孔位于对应于要使用重新路由元件的半导体器件的接合焊盘的位置的位置处。 与相应的导电通孔连通的导电元件将接合焊盘位置重新路由到与被重新路由的半导体器件的一个外围边缘或两个相邻外围边缘相邻的相应接触焊盘位置。 重新路由元件对于重新布置半导体器件的中心位置的接合焊盘以及将半导体器件的接合焊盘的外围位置重新路由到其一个或两个相邻的外围边缘是特别有用的。 还公开了用于设计和使用重新路由元件的方法，半导体器件组件包括一个或多个重新布线元件。