公开(公告)号：US20180269312A1

公开(公告)日：2018-09-20

申请号：US15458457

申请日：2017-03-14

申请人： GLOBALFOUNDRIES Inc.

发明人： Ruilong Xie ,  Chun-chen Yeh ,  Kangguo Cheng ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L29/10 ,  H01L21/311 ,  H01L21/324

CPC分类号： H01L29/66795 ,  H01L21/324 ,  H01L29/1037 ,  H01L29/41791 ,  H01L29/66553 ,  H01L29/785 ,  H01L2029/7858

摘要： Device structures and fabrication methods for a vertical field-effect transistor. A semiconductor fin is formed that projects from a first source/drain region. A first spacer layer is formed on the first source/drain region. A dielectric layer is formed that extends in the vertical direction from the first spacer layer to a top surface of the semiconductor fin. The dielectric layer is recessed in the vertical direction, and a second spacer layer is formed on the recessed dielectric layer such that the dielectric layer is located in the vertical direction between the first spacer layer and the second spacer layer. After the dielectric layer is removed to open a space between the first spacer layer and the second spacer layer, a gate electrode is formed in the space. The vertical field-effect transistor has a gate length that is equal to a thickness of the recessed dielectric layer.

公开(公告)号：US10069015B2

公开(公告)日：2018-09-04

申请号：US15276372

申请日：2016-09-26

申请人： International Business Machines Corporation ,  Globalfoundries Inc.

发明人： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

摘要： In one aspect, a method of forming a semiconductor device includes the steps of: forming an alternating series of sacrificial/active layers on a wafer and patterning it into at least one nano device stack; forming a dummy gate on the nano device stack; patterning at least one upper active layer in the nano device stack to remove all but a portion of the at least one upper active layer beneath the dummy gate; forming spacers on opposite sides of the dummy gate covering the at least one upper active layer that has been patterned; forming source and drain regions on opposite sides of the nano device stack, wherein the at least one upper active layer is separated from the source and drain regions by the spacers; and replacing the dummy gate with a replacement gate. A masking process is also provided to tailor the effective device width of select devices.

公开(公告)号：US20180212024A1

公开(公告)日：2018-07-26

申请号：US15925051

申请日：2018-03-19

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries Inc.

发明人： Kangguo Cheng ,  Xin Miao ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L21/02 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/265

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/26566 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： A method of making a nanowire device includes disposing a first nanowire stack over a substrate, the first nanowire stack including alternating layers of a first and second semiconducting material, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; disposing a second nanowire stack over the substrate, the second nanowire stack including alternating layers of the first and second semiconducting materials, the first semiconducting material contacting the substrate and the second semiconducting material being an exposed surface; forming a first gate spacer along a sidewall of a first gate region on the first nanowire stack and a second gate spacer along a sidewall of a second gate region on the second nanowire stack; oxidizing a portion of the first nanowire stack within the first gate spacer; and removing the first semiconducting material from the first nanowire stack and the second nanowire stack.

公开(公告)号：US10014299B2

公开(公告)日：2018-07-03

申请号：US15170134

申请日：2016-06-01

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Xiuyu Cai ,  Sanjay C. Mehta ,  Tenko Yamashita

IPC分类号： H01L27/00 ,  H01L27/092 ,  H01L29/16 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/311

CPC分类号： H01L27/0924 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L29/16 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

摘要： A method for fabricating a field effect transistor device comprises forming a fin on a substrate, forming a first dummy gate stack and a second dummy gate stack over the fin, forming spacers adjacent to the fin, the first dummy gate stack, and the second dummy gate stack, etching to remove portions of the fin and form a first cavity partially defined by the spacers, depositing an insulator material in the first cavity, patterning a mask over the first dummy gate stack and portions of the fin, etching to remove exposed portions of the insulator material, and epitaxially growing a first semiconductor material on exposed portions of the fin.

公开(公告)号：US09984893B2

公开(公告)日：2018-05-29

申请号：US15483346

申请日：2017-04-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GlobalFoundries, Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/06 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/66 ,  H01L21/306

CPC分类号： H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

摘要： A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first and second cut fin, the first cut fin having a first and second fin end and the second cut fin having a first and second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

公开(公告)号：US09905671B2

公开(公告)日：2018-02-27

申请号：US14829843

申请日：2015-08-19

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L21/768 ,  H01L29/78 ,  H01L29/417 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L29/66553 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28079 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

摘要： A method of making a semiconductor device includes patterning a fin in a substrate; forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall; removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer having a first spacer portion and a second spacer portion; forming a source/drain contact over at least one of the source/drain regions; recessing the source/drain contact and forming a via contact over the source/drain contact; and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion; wherein the first spacer portion isolates the first gate contact portion from the source/drain contact, and the second spacer portion isolates the second gate contact portion from the source/drain contact.

公开(公告)号：US09799746B2

公开(公告)日：2017-10-24

申请号：US15278925

申请日：2016-09-28

申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/06 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L29/4991 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/66568

摘要： Techniques for preventing leakage of contact material into air-gap spacers during contact formation. For example, a method comprises forming a contact trench on a semiconductor structure over an air-gap spacer and depositing a liner in the contact trench. The liner deposition material fills a portion of the air-gap spacer pinching off the contact trench to the air-gap spacer.

公开(公告)号：US09647093B2

公开(公告)日：2017-05-09

申请号：US15073065

申请日：2016-03-17

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31 ,  H01L21/324 ,  H01L29/66795

摘要： A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin.

公开(公告)号：US20170125539A1

公开(公告)日：2017-05-04

申请号：US15233315

申请日：2016-08-10

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Kangguo Cheng ,  Ruilong Xie ,  Tenko Yamashita

IPC分类号： H01L29/49 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC分类号： H01L29/4991 ,  H01L21/28114 ,  H01L21/28132 ,  H01L21/283 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/764 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76879 ,  H01L21/823468 ,  H01L21/823864 ,  H01L23/5226 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/515 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides of the channel region. The semiconductor device may further include a composite gate sidewall spacer present on a sidewall of the gate structure. The composite gate sidewall spacer may include a first composition portion having an air gap encapsulated therein, and a second composition portion that is entirely solid and present atop the first composition portion.

公开(公告)号：US20170125535A1

公开(公告)日：2017-05-04

申请号：US15272919

申请日：2016-09-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

发明人： Hiroaki Niimi ,  Shariq Siddiqui ,  Tenko Yamashita

IPC分类号： H01L29/45 ,  H01L29/161 ,  H01L29/417 ,  H01L27/092 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/08 ,  H01L21/768

CPC分类号： H01L29/45 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/285 ,  H01L21/28512 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76895 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/535 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7848

摘要： An electrical device including a first semiconductor device having a silicon and germanium containing source and drain region, and a second semiconductor device having a silicon containing source and drain region. A first device contact to at least one of said silicon and germanium containing source and drain region of the first semiconductor device including a metal liner of an aluminum titanium and silicon alloy and a first tungsten fill. A second device contact is in contact with at least one of the silicon containing source and drain region of the second semiconductor device including a material stack of a titanium oxide layer and a titanium layer. The second device contact may further include a second tungsten fill.