公开(公告)号：US09495989B2

公开(公告)日：2016-11-15

申请号：US13760154

申请日：2013-02-06

Applicant: International Business Machines Corporation

Inventor： Robert E. Fontana, Jr. ,  William J. Gallagher ,  Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

IPC: B32B15/04 ,  G11B5/66 ,  C25D7/00 ,  C25D7/12 ,  C25D3/54 ,  C25D5/10 ,  C25D5/14 ,  C25D9/10 ,  H01F10/32 ,  C25D3/58 ,  C25D5/18 ,  C25D5/50

CPC classification number: H01F10/3231 ,  C25D3/54 ,  C25D3/58 ,  C25D5/10 ,  C25D5/14 ,  C25D5/18 ,  C25D5/50 ,  C25D7/001 ,  C25D7/123 ,  C25D9/08 ,  C25D9/10 ,  C25D17/001 ,  G11B5/66 ,  H01F3/02 ,  H01F10/3236 ,  H01F10/324 ,  H01F10/325 ,  H01F10/3254 ,  H01F41/02

Abstract: A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.

Abstract translation: 层叠结构包括第一磁性层，第二磁性层，设置在第一和第二磁性层之间的第一间隔件和设置在第二磁性层上的第二间隔件。

公开(公告)号：US09384879B2

公开(公告)日：2016-07-05

申请号：US14155552

申请日：2014-01-15

Applicant: International Business Machines Corporation

Inventor： Philipp Herget ,  Eugene J. O'Sullivan ,  Lubomyr T. Romankiw ,  Naigang Wang ,  Bucknell C. Webb

IPC: H01L29/82 ,  H01F7/02 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L27/22 ,  G11B5/3163 ,  H01F1/14708 ,  H01F7/021 ,  H01F10/14 ,  H01F27/24 ,  H01F27/2804 ,  H01F2027/2809 ,  H01L27/0641 ,  H01L27/224 ,  H01L28/10 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A mechanism is provided for an integrated laminated magnetic device. A substrate and a multilayer stack structure form the device. The multilayer stack structure includes alternating magnetic layers and diode structures formed on the substrate. Each magnetic layer in the multilayer stack structure is separated from another magnetic layer in the multilayer stack structure by a diode structure.

Abstract translation: 提供了一种用于集成层压磁性装置的机构。 基板和多层堆叠结构形成该装置。 多层堆叠结构包括在基板上形成的交替磁层和二极管结构。 多层堆叠结构中的每个磁性层通过二极管结构与多层堆叠结构中的另一磁性层分离。

公开(公告)号：US20150287772A1

公开(公告)日：2015-10-08

申请号：US14745703

申请日：2015-06-22

Applicant: International Business Machines Corporation

Inventor： Naigang Wang ,  Bucknell C. Webb

IPC: H01L49/02 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L21/31 ,  H01L21/31111 ,  H01L21/3205 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A mechanism is provided for integrating an inductor into a semiconductor. A circular or other closed loop trench is formed in a substrate with sidewalls connected by a bottom surface in the substrate. A first insulator layer is deposited on the sidewalls of the trench so as to coat the sidewalls and the bottom surface. A conductor layer is deposited on the sidewalls and the bottom surface of the trench so as to coat the first insulator layer in the trench such that the conductor layer is on top of the first insulator layer in the trench. A first magnetic layer is deposited on the sidewalls and bottom surface of the trench so as to coat the first insulator layer in the trench without filling the trench. The first magnetic layer deposited on the sidewalls forms an inner closed magnetic loop and an outer closed magnetic loop within the trench.

公开(公告)号：US08759963B2

公开(公告)日：2014-06-24

申请号：US14043137

申请日：2013-10-01

Applicant: International Business Machines Corporation

Inventor： Jae-Woong Nah ,  Katsuyuki Sakuma ,  Bucknell C. Webb

IPC: H01L23/02

CPC classification number: H01L21/50 ,  H01L21/561 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06582 ,  H01L2224/32145 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2224/81 ,  H01L2924/014

Abstract: A template having tapered openings can be employed to enable injection of underfill material through gaps having a width less than a lateral dimension of an injector needle for the underfill material. Each tapered opening has a first lateral dimension on an upper side and a second lateral dimension on a lower side. Compliant material portions can be employed to accommodate variations in distance between the template and stacked semiconductor chips and/or an injector head. Optionally, another head can be employed to apply compressed gas to push out the underfill material after the underfill material is applied to the gaps. Multiple injector heads can be employed to simultaneously inject the underfill material at different sites. An adhesive layer can be substituted for the at least one lower compliant material portion.

Abstract translation: 可以使用具有锥形开口的模板，以使得能够通过具有小于底部填充材料的注射器针的横向尺寸的间隙的间隙注入底部填充材料。 每个锥形开口具有在上侧上的第一横向尺寸和在下侧上的第二横向尺寸。 可以采用符合材料的部分来适应模板和堆叠的半导体芯片和/或注射器头之间的距离的变化。 可选地，在将底部填充材料施加到间隙之后，可以使用另一个头部来施加压缩气体以推出底部填充材料。 可以使用多个注射器头来同时将底部填充材料注入不同的位置。 粘合剂层可以代替至少一个下顺应材料部分。

公开(公告)号：US20140087557A1

公开(公告)日：2014-03-27

申请号：US13626025

申请日：2012-09-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Jeffrey P. Gambino ,  Cameron E. Luce ,  Daniel S. Vanslette ,  Bucknell C. Webb

IPC: H01L21/768

CPC classification number: H01L23/5384 ,  G06F17/5045 ,  G06F17/5077 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/562 ,  H01L27/0207 ,  H01L2224/48091 ,  H01L2224/73257 ,  H01L2924/1305 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Disclosed herein are through silicon vias (TSVs) and contacts formed on a semiconductor material, methods of manufacturing, and design structures. The method includes forming a contact hole in a dielectric material formed on a substrate. The method further includes forming a via in the substrate and through the dielectric material. The method further includes lining the contact hole and the dielectric material with a metal liner using a deposition technique that will avoid formation of the liner in the viaformed in the substrate. The method further includes filling the contact hole and the via with a metal such that the metal is formed on the liner in the contact hole and directly on the substrate in the via.

公开(公告)号：US20210351043A1

公开(公告)日：2021-11-11

申请号：US16869744

申请日：2020-05-08

Applicant: International Business Machines Corporation

Inventor： Jae-Woong Nah ,  Evan Colgan ,  Robert P. Kuder, II ,  James L. Speidell ,  Bucknell C. Webb

IPC: H01L21/48 ,  H01L23/473 ,  H01L21/67

Abstract: A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.

公开(公告)号：US11088097B2

公开(公告)日：2021-08-10

申请号：US16414042

申请日：2019-05-16

Applicant: International Business Machines Corporation

Inventor： Bucknell C. Webb

IPC: H01L23/66 ,  H01Q1/22 ,  H01Q1/38 ,  H01Q1/40 ,  H01Q9/06

Abstract: An electronic package apparatus is formed from a semiconductor substrate having a cavity formed therein. The cavity has a top surface, a bottom surface and a sidewall surface, and a spacer extending from the bottom surface to the top surface. The spacer is formed from a dielectric material and has at least one lateral dimension less than 0.1 cm.

公开(公告)号：US10173888B2

公开(公告)日：2019-01-08

申请号：US15650788

申请日：2017-07-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Bucknell C. Webb

Inventor： Bucknell C. Webb

IPC: B81B3/00 ,  B81C1/00 ,  G01R33/02 ,  G01R33/028 ,  H01H51/22

Abstract: Deep via technology is used to construct an integrated silicon cantilever and cavity oriented in a vertical plane which creates an electrostatically-switched MEMS switch in a small wafer area. Another embodiment is a small wafer area electrostatically-switched, vertical-cantilever MEMS switch wherein the switch cavity is etched within a volume defined by walls grown internally within a silicon substrate using through vias.

公开(公告)号：US20180098432A1

公开(公告)日：2018-04-05

申请号：US15821432

申请日：2017-11-22

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Qianwen Chen ,  Bing Dang ,  John U. Knickerbocker ,  Minhua Lu ,  Robert J. Polastre ,  Bucknell C. Webb

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/30 ,  H05K1/03 ,  H05K3/34

CPC classification number: H05K1/189 ,  G01R31/2818 ,  G01R31/309 ,  G01R31/44 ,  H05K1/0268 ,  H05K1/0274 ,  H05K1/0393 ,  H05K1/111 ,  H05K3/0026 ,  H05K3/0052 ,  H05K3/305 ,  H05K3/341 ,  H05K3/3494 ,  H05K13/0069 ,  H05K2201/09072 ,  H05K2201/10015 ,  H05K2201/10037 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10121 ,  H05K2201/10522 ,  H05K2203/107 ,  H05K2203/162

Abstract: An electro-optical module assembly is provided that includes a flexible substrate having a first surface and a second surface opposite the first surface, wherein the flexible substrate contains an opening located therein that extends from the first surface to the second surface. An optical component is located on the second surface of the flexible substrate and is positioned to have a surface exposed by the opening. At least one electronic component is located on a first portion of the first surface of the flexible substrate, and at least one micro-energy source is located on a second portion of the first surface of the flexible substrate.

公开(公告)号：US20170324068A1

公开(公告)日：2017-11-09

申请号：US15416564

申请日：2017-01-26

Applicant: International Business Machines Corporation

Inventor： Paul S. Andry ,  Bing Dang ,  John U. Knickerbocker ,  Yang Liu ,  Jae-Woong Nah ,  Adinath Narasgond ,  Bucknell C. Webb

IPC: H01M2/02 ,  H01M2/10

CPC classification number: H01M2/0207 ,  H01M2/1061 ,  H01M6/40 ,  H01M10/0436 ,  H01M2220/30

Abstract: A micro-battery is provided in which a metallic sealing layer is used to provide a hermetic seal between an anode side of the micro-battery and the cathode side of the micro-battery. In accordance with the present application, the metallic sealing layer is formed around a perimeter of each metallic anode structure located on the anode side and then the metallic sealing layer is bonded to a solderable metal layer of a wall structure present on the cathode side. The wall structure contains a cavity that exposes a metallic current collector structure, the cavity is filled with battery materials.