公开(公告)号：US20240347590A1

公开(公告)日：2024-10-17

申请号：US18755306

申请日：2024-06-26

申请人： Intel Corporation

发明人： Bhaskar Jyoti Krishnatreya ,  Guruprasad Arakere ,  Nitin Ashok Deshpande ,  Mohammad Enamul Kabir ,  Omkar Gopalkrishna Karhade ,  Keith Edward Zawadzki ,  Trianggono S. Widodo

IPC分类号： H01L29/06 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/78 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L29/0657 ,  H01L21/78 ,  H01L23/562 ,  H01L25/0655 ,  H01L21/30625 ,  H01L21/3065 ,  H01L24/08 ,  H01L2224/08221

摘要： Systems, apparatus, articles of manufacture, and methods to reduce stress in integrated circuit packages are disclosed. An example semiconductor chip includes: a front surface; a back surface opposite the front surface; a first lateral surface extending between the front surface and the back surface; a second lateral surface extending between the front surface and the back surface; and a curved fillet at an intersection between the first lateral surface and the second lateral surface.

公开(公告)号：US20240063178A1

公开(公告)日：2024-02-22

申请号：US17821001

申请日：2022-08-19

申请人： Intel Corporation

发明人： Jimin Yao ,  Adel A. Elsherbini ,  Xavier Francois Brun ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Yi Shi ,  Tushar Talukdar ,  Feras Eid ,  Mohammad Enamul Kabir ,  Omkar G. Karhade ,  Bhaskar Jyoti Krishnatreya

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L25/0652 ,  H01L23/3107 ,  H01L24/16 ,  H01L24/08 ,  H01L2225/06548 ,  H01L2224/16227 ,  H01L2224/08145 ,  H01L2224/13116 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13109 ,  H01L2224/13118 ,  H01L24/13 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05613 ,  H01L2224/05609 ,  H01L2224/05605 ,  H01L24/05

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die and a through-dielectric via (TDV) surrounded by a dielectric material in a first layer, where the TDV has a greater width at a first surface and a smaller width at an opposing second surface of the first layer; a second die, surrounded by the dielectric material, in a second layer on the first layer, where the first die is coupled to the second die by interconnects having a pitch of less than 10 microns, and the dielectric material around the second die has an interface seam extending from a second surface of the second layer towards an opposing first surface of the second layer with an angle of less than 90 degrees relative to the second surface; and a substrate on and coupled to the second layer.

公开(公告)号：US20240063143A1

公开(公告)日：2024-02-22

申请号：US17891690

申请日：2022-08-19

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Lance C. Hibbeler ,  Omkar Karhade ,  Chytra Pawashe ,  Kimin Jun ,  Feras Eid ,  Shawna Liff ,  Mohammad Enamul Kabir ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Wenhao Li

IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/562 ,  H01L25/0657 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06548 ,  H01L2225/06582 ,  H01L2924/3511

摘要： Techniques and mechanisms to mitigate warping of a composite chiplet. In an embodiment, multiple via structures each extend through an insulator material in one of multiple levels of a composite chiplet. The insulator material extends around an integrated circuit (IC) component in the level. For a given one of the multiple via structures, a respective annular structure extends around the via structure to mitigate a compressive (or tensile) stress due to expansion (or contraction) of the via structure. In another embodiment, the composite chiplet additionally or alternatively comprises a structural support layer on the multiple levels, wherein the structural support layer has formed therein or thereon dummy via structures or a warpage compensation film.

公开(公告)号：US20240063142A1

公开(公告)日：2024-02-22

申请号：US17891666

申请日：2022-08-19

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Tushar Talukdar ,  Botao Zhang ,  Yi Shi ,  Haris Khan Niazi ,  Feras Eid ,  Nagatoshi Tsunoda ,  Xavier Brun ,  Mohammad Enamul Kabir ,  Omkar Karhade ,  Shawna Liff ,  Jiraporn Seangatith

IPC分类号： H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/562 ,  H01L23/367 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/486 ,  H01L21/565 ,  H01L25/0655 ,  H01L25/50

摘要： Multi-die packages including IC die crack mitigation features. Prior to the bonding of IC dies to a host substrate, the IC dies may be shaped, for example with a corner radius or chamfer. After bonding the shaped IC dies, a fill comprising at least one inorganic material may be deposited over the IC dies, for example to backfill a space between adjacent IC dies. With the benefit of a greater IC die sidewall slope and/or smoother surface topology associated with the shaping process, occurrences of stress cracking within the fill and concomitant damage to the IC dies may be reduced. Prior to depositing a fill, a barrier layer may be deposited over the IC die to prevent cracks that might form in the fill material from propagating into the IC die.

公开(公告)号：US20240063089A1

公开(公告)日：2024-02-22

申请号：US17891738

申请日：2022-08-19

申请人： Intel Corporation

发明人： Adel Elsherbini ,  Wenhao Li ,  Bhaskar Jyoti Krishnatreya ,  Debendra Mallik ,  Krishna Vasanth Valavala ,  Lei Jiang ,  Yoshihiro Tomita ,  Omkar Karhade ,  Haris Khan Niazi ,  Tushar Talukdar ,  Mohammad Enamul Kabir ,  Xavier Brun ,  Feras Eid

IPC分类号： H01L23/46

CPC分类号： H01L23/46 ,  G02B6/4268

摘要： Microelectronic devices, assemblies, and systems include a multichip composite device having one or more integrated circuit dies bonded to a base die and an inorganic dielectric material adjacent the integrated circuit dies and over the base die. The multichip composite device includes a dummy die, dummy vias, or integrated fluidic cooling channels laterally adjacent the integrated circuit dies to conduct heat from the base die.