公开(公告)号：US20180233447A1

公开(公告)日：2018-08-16

申请号：US15952935

申请日：2018-04-13

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM ,  Hong SHEN ,  Zhuowen SUN ,  Liang WANG ,  Guilian GAO

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L21/8234

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20180124927A1

公开(公告)日：2018-05-03

申请号：US15858791

申请日：2017-12-29

Applicant: INVENSAS CORPORATION

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H05K3/40 ,  H01L23/00 ,  H05K1/11 ,  H05K3/34

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

公开(公告)号：US20170278787A1

公开(公告)日：2017-09-28

申请号：US15619160

申请日：2017-06-09

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Arkalgud R. SITARAM ,  Hong SHEN ,  Zhuowen SUN ,  Liang WANG ,  Guilian GAO

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/8234 ,  H01L21/768

CPC classification number: H01L23/5223 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US20160379885A1

公开(公告)日：2016-12-29

申请号：US14749529

申请日：2015-06-24

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH ,  Guilian GAO ,  Liang WANG ,  Hong SHEN ,  Arkalgud R. SITARAM

IPC: H01L21/82 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/522

CPC classification number: H01L21/82 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L24/98 ,  H01L2224/04105 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/3512

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Abstract translation: 一种形成该器件的器件和方法，该器件包括形成在衬底器件的衬底中的腔体，该衬底器件还包括形成在衬底中的导电通孔。 芯片器件，晶片和其他衬底器件可以安装到衬底器件上。 可以在衬底装置上形成封装层和材料以便填充空腔。

公开(公告)号：US20160293534A1

公开(公告)日：2016-10-06

申请号：US15181872

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Zhuowen Sun ,  Charles G. Woychik ,  Arkalgud Sitaram

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/49833 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/1615 ,  H01L2924/16153 ,  H01L2924/16251 ,  H01L2924/181 ,  H05K1/0271 ,  H05K1/111 ,  H05K1/141 ,  H05K1/181 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combined interposer (120) includes multiple constituent interposers (120.i), each with its own substrate (120.iS) and with a circuit layer (e.g. redistribution layer) on top and/or bottom of the substrate. The top circuit layers can be part of a common circuit layer (120R.T) which can interconnect different interposers. Likewise, the bottom circuit layers can be part of a common circuit layer (120R.B). The constituent interposer substrates (120.iS) are initially part of a common wafer, and the common top circuit layer is fabricated before separation of the constituent interposer substrates from the wafer. Use of separated substrates reduces stress compared to use of a single large substrate. Other features are also provided.

公开(公告)号：US20180076278A1

公开(公告)日：2018-03-15

申请号：US15804847

申请日：2017-11-06

Applicant: INVENSAS CORPORATION

Inventor： Liang WANG ,  Hong SHEN ,  Rajesh KATKAR

IPC: H01L49/02 ,  H01L21/56 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L25/16 ,  H01L25/11 ,  H01L25/10

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: A method for making an integrated circuit package includes providing a handle wafer having a first region defining a cavity. A capacitor is formed in the first region. The capacitor has a pair of electrodes, each coupled to one of a pair of conductive pads, at least one of which is disposed on a lower surface of the handle wafer. An interposer having an upper surface with a conductive pad and at least one semiconductor die disposed thereon is also provided. The die has an integrated circuit that is electroconductively coupled to a redistribution layer (RDL) of the interposer. The lower surface of the handle wafer is bonded to the upper surface of the interposer such that the die is disposed below or within the cavity and the electroconductive pad of the handle wafer is bonded to the electroconductive pad of the interposer in a metal-to-metal bond.

公开(公告)号：US20170125331A1

公开(公告)日：2017-05-04

申请号：US15403679

申请日：2017-01-11

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Liang WANG ,  Gabriel Z. GUEVARA ,  Rajesh KATKAR ,  Cyprian Emeka UZOH ,  Laura Wills MIRKARIMI

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US20160322456A1

公开(公告)日：2016-11-03

申请号：US15207837

申请日：2016-07-12

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H01L49/02

CPC classification number: H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

公开(公告)号：US20160192496A1

公开(公告)日：2016-06-30

申请号：US14942781

申请日：2015-11-16

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L24/81 ,  H01L2224/81193 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/3431

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Abstract translation: 接触焊盘包括可钎焊熔融焊料（130）的焊料可润湿多孔网（310），从而限制焊料的横向扩展，从而防止相邻接触焊盘之间的焊料桥接。

公开(公告)号：US20150262902A1

公开(公告)日：2015-09-17

申请号：US14214365

申请日：2014-03-14

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Charles G. Woychik ,  Arkalgud R. Sitaram

IPC: H01L23/31 ,  H01L21/56

CPC classification number: H01L23/055 ,  H01L21/2885 ,  H01L21/4803 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3107 ,  H01L23/315 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.

Abstract translation: 具有集成电路的模具（110）附接到布线基板（120），可能是插入件，并且被附接到布线基板的保护基板（410）保护。 模具位于保护衬底中的空腔中（模具可能突出出腔体）。 在一些实施例中，每个空腔表面在模具上施加压力以加强模具与布线基板的机械连接，以在模具和环境（或散热器）之间提供良好的导热性以抵抗模具翘曲，并且可能 减小垂直尺寸。 保护衬底可以具有或不具有连接到管芯或布线衬底的其自身的电路。 还提供其他功能。