公开(公告)号：US20160079093A1

公开(公告)日：2016-03-17

申请号：US14488187

申请日：2014-09-16

Applicant: Invensas Corporation

Inventor： Eric S. TOSAYA ,  Rajesh KATKAR ,  Liang WANG ,  Cyprian Emeka UZOH

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/13 ,  H01L23/3178 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06102 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.

Abstract translation: 微电子部件（110,120）具有凹陷在空腔（410）中并被底部填充带（130）覆盖的接触垫（110C，120C，920C）。 空腔在底部填充带下方具有空隙（410V）。 另一微电子元件的突出的接触垫破坏了底部填充带进入腔并结合到凹陷接触垫。 该空隙有助于破裂底部填充带，从而减少两个接触垫之间的底部填充残余物的量并改善接触电阻。 还提供了一种微电子部件，其具有带有空腔的基板，并且具有延伸到空腔中的贯穿基板。 还提供其他功能。

公开(公告)号：US20150262910A1

公开(公告)日：2015-09-17

申请号：US14206756

申请日：2014-03-12

Applicant: Invensas Corporation

Inventor： Zhuowen SUN ,  Cyprian Emeka UZOH ,  Yong CHEN

IPC: H01L23/48 ,  H01L23/532

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/5384 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

Abstract translation: 公开了一般涉及基板的装置。 在这种装置中，衬底具有与第一表面相对的第一表面和第二表面。 第一表面和第二表面限定基底的厚度。 通孔结构从衬底的第一表面延伸到衬底的第二表面。 通孔结构具有位于第一表面处或靠近第一表面的第一端子和位于第二表面处或靠近第二表面处的第二端子，该第二端子由从第一端子延伸到第二端子的通孔结构的导电构件提供。 通孔结构的阻挡层设置在导电部件的至少一部分和基板之间。 阻挡层具有被配置为当信号通过通孔结构的导电构件时抵消导电构件和衬底之间的电容的导电性。

公开(公告)号：US20150155241A1

公开(公告)日：2015-06-04

申请号：US14095704

申请日：2013-12-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH

IPC: H01L23/00 ,  H01L21/3205

CPC classification number: H01L23/562 ,  H01L21/32051 ,  H01L21/78 ,  H01L22/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2924/12042 ,  H01L2924/00

Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

Abstract translation: 为了减少晶片的至少一个区域中的翘曲，形成应力/翘曲管理层（810）以使现有翘曲的方向超平衡并改变。 例如，如果该地区的中部相对于该地区的边界膨胀，该区域的中部可能会向下膨胀，反之亦然。 然后处理压力/翘曲管理层以减少过度平衡。 例如，应力/管理层可以在选定位置从晶片剥离，或者可以在层中形成凹陷，或者可以在该层中引起相变。 在其它实施例中，该层是钽 - 铝，其可能或可能不会使翘曲过度平衡; 这一层被认为是由于结晶相依赖的应力而减少翘曲，其动态地适应温度变化，以减少翘曲（可能通过热循环保持晶片平坦）。 还提供其他功能。

公开(公告)号：US20170125331A1

公开(公告)日：2017-05-04

申请号：US15403679

申请日：2017-01-11

Applicant: Invensas Corporation

Inventor： Hong SHEN ,  Liang WANG ,  Gabriel Z. GUEVARA ,  Rajesh KATKAR ,  Cyprian Emeka UZOH ,  Laura Wills MIRKARIMI

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L23/49822 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/85399

Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

公开(公告)号：US20160322456A1

公开(公告)日：2016-11-03

申请号：US15207837

申请日：2016-07-12

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H01L49/02

CPC classification number: H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

公开(公告)号：US20160192496A1

公开(公告)日：2016-06-30

申请号：US14942781

申请日：2015-11-16

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H05K1/18 ,  H05K3/34 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K3/4007 ,  H01L24/81 ,  H01L2224/81193 ,  H01L2924/3841 ,  H05K1/111 ,  H05K3/3431

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

Abstract translation: 接触焊盘包括可钎焊熔融焊料（130）的焊料可润湿多孔网（310），从而限制焊料的横向扩展，从而防止相邻接触焊盘之间的焊料桥接。

公开(公告)号：US20150325543A1

公开(公告)日：2015-11-12

申请号：US14275514

申请日：2014-05-12

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Cyprian Emeka UZOH

IPC: H01L23/00 ,  B23K26/32 ,  H05K1/14 ,  H05K3/34 ,  H05K1/11

CPC classification number: H01L24/14 ,  B23K1/0016 ,  B23K3/0623 ,  B23K35/0244 ,  B23K35/0266 ,  B23K2101/40 ,  H01L21/02225 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/73 ,  H01L24/742 ,  H01L24/81 ,  H01L24/83 ,  H01L24/98 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/0333 ,  H01L2224/0391 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/0508 ,  H01L2224/051 ,  H01L2224/05567 ,  H01L2224/056 ,  H01L2224/06102 ,  H01L2224/10145 ,  H01L2224/11001 ,  H01L2224/11005 ,  H01L2224/11009 ,  H01L2224/111 ,  H01L2224/11318 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13078 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/131 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13169 ,  H01L2224/1319 ,  H01L2224/13561 ,  H01L2224/13562 ,  H01L2224/136 ,  H01L2224/13609 ,  H01L2224/13611 ,  H01L2224/1405 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16145 ,  H01L2224/16147 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1701 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17505 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/75253 ,  H01L2224/81138 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/8122 ,  H01L2224/81224 ,  H01L2224/81815 ,  H01L2224/81825 ,  H01L2224/8385 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/115 ,  H05K1/144 ,  H05K3/341 ,  H05K2201/09572 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2224/81 ,  H01L2224/83

Abstract: In some embodiments, to increase the height-to-pitch ratio of a solder connection that connects different structures with one or more solder balls, only a portion of a solder ball's surface is melted when the connection is formed on one structure and/or when the connection is being attached to another structure. In some embodiments, non-solder balls are joined by an intermediate solder ball (140i). A solder connection may be surrounded by a solder locking layer (1210) and may be recessed in a hole (1230) in that layer. Other features are also provided.

Abstract translation: 在一些实施例中，为了增加将不同结构与一个或多个焊球连接的焊料连接的高度与间距比，当连接形成在一个结构上时和/或当 连接正在附加到另一个结构。 在一些实施例中，非焊球通过中间焊球（140i）连接。 焊料连接可以被焊料锁定层（1210）包围，并且可以凹陷在该层中的孔（1230）中。 还提供其他功能。

公开(公告)号：US20150255429A1

公开(公告)日：2015-09-10

申请号：US14201585

申请日：2014-03-07

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Sitaram ARKALGUD ,  Cyprian Emeka UZOH

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/367 ,  H01L25/00 ,  H01L23/48 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L23/538 ,  H01L21/768

CPC classification number: H01L25/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/31105 ,  H01L21/76897 ,  H01L21/76898 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L23/5386 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.

Abstract translation: 装置一般涉及三维堆叠集成电路。 在这种装置中，三维堆叠集成电路具有至少第一管芯和第二管芯，使用管芯到管芯互连彼此互连。 第一管芯的衬底具有至少一个热通孔结构，其从衬底的下表面朝向衬底的阱延伸，而不延伸到阱并且不延伸通过衬底。 所述至少一个热通孔结构的第一端至少足够靠近所述衬底的阱，用于将热量传导出来。 衬底具有从衬底的下表面延伸到衬底的上表面的至少一个穿过衬底通孔结构。 所述至少一个热通孔结构的第二端与所述第二管芯的至少一个通孔通孔结构耦合以进行导热。

公开(公告)号：US20170084582A1

公开(公告)日：2017-03-23

申请号：US15360073

申请日：2016-11-23

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/18 ,  H01L24/42 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/05599 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/4911 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: A method of forming a semiconductor package includes providing a substrate having one or more conductive elements disposed therein. Each conductive element extends from a first surface of the substrate toward a second surface of the substrate extending beyond the second surface. The second surface comprises one or more substrate regions not occupied by a conductive element. A first die is attached within a substrate region, and the first die is coupled to at least one of the conductive elements. The first die may be coupled to at least one of the conductive elements by a wire bond connection. Alternatively, an RDL is formed over the second surface, and the first die is coupled to at least one conductive element through the RDL. A second die may be attached to an outer surface of the RDL, and the second die is electrically coupled to the first die through the RDL.

公开(公告)号：US20160293556A1

公开(公告)日：2016-10-06

申请号：US15181861

申请日：2016-06-14

Applicant: Invensas Corporation

Inventor： Cyprian Emeka UZOH

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/78 ,  H01L21/3205

CPC classification number: H01L23/562 ,  H01L21/32051 ,  H01L21/78 ,  H01L22/12 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/0345 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2924/12042 ,  H01L2924/00

Abstract: To reduce warpage in at least one area of a wafer, a stress/warpage management layer (810) is formed to over-balance and change the direction of the existing warpage. For example, if the middle of the area was bulging up relative to the area's boundary, the middle of the area may become bulging downward, or vice versa. Then the stress/warpage management layer is processed to reduce the over-balancing. For example, the stress/management layer can be debonded from the wafer at selected locations, or recesses can be formed in the layer, or phase changes can be induced in the layer. In other embodiments, this layer is tantalum-aluminum that may or may not over-balance the warpage; this layer is believed to reduce warpage due to crystal-phase-dependent stresses which dynamically adjust to temperature changes so as to reduce the warpage (possibly keeping the wafer flat through thermal cycling). Other features are also provided.

Abstract translation: 为了减少晶片的至少一个区域中的翘曲，形成应力/翘曲管理层（810）以使现有翘曲的方向超平衡并改变。 例如，如果该地区的中部相对于该地区的边界膨胀，该区域的中部可能会向下膨胀，反之亦然。 然后处理压力/翘曲管理层以减少过度平衡。 例如，应力/管理层可以在选定位置从晶片剥离，或者可以在层中形成凹陷，或者可以在该层中引起相变。 在其它实施例中，该层是钽 - 铝，其可能或可能不会使翘曲过度平衡; 这一层被认为是由于结晶相依赖的应力而减少翘曲，其动态地适应温度变化，以减少翘曲（可能通过热循环保持晶片平坦）。 还提供其他功能。