公开(公告)号：US20160276294A1

公开(公告)日：2016-09-22

申请号：US15165837

申请日：2016-05-26

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Laura Wills MIRKARIMI ,  Arkalgud SITARAM ,  Charles G. WOYCHIK

IPC: H01L23/00 ,  H01L21/66 ,  H01L23/367 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16176 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

公开(公告)号：US20160254205A1

公开(公告)日：2016-09-01

申请号：US15151176

申请日：2016-05-10

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Charles G. WOYCHIK ,  Cyprian Emeka UZOH

IPC: H01L23/31 ,  H01L25/00 ,  H01L21/48 ,  H01L21/52 ,  H01L21/54 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L23/3178 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/54 ,  H01L21/563 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06593 ,  H01L2924/15153 ,  H01L2924/15156 ,  H01L2924/014

Abstract: A device and method for localizing underfill includes a substrate, a plurality of dies, and underfill material. The substrate includes a plurality of contacts and a plurality of cavities separated by a plurality of mesas. The plurality of dies is mounted to the substrate using the plurality of contacts. The underfill material is located between the substrate and the dies. The underfill material is localized into a plurality of regions using the mesas. Each of the contacts is located in a respective one of the cavities. In some embodiments, the substrate further includes a plurality of channels interconnecting the cavities. In some embodiments, the substrate further includes a plurality of intra-cavity mesas for further localizing the underfill material. In some embodiments, outer edges of a first one of the dies rest on first mesas located on edges of a first one of the cavities.

Abstract translation: 用于定位底部填充物的装置和方法包括基底，多个模具和底部填充材料。 衬底包括多个触点和由多个台面隔开的多个空腔。 使用多个触点将多个模具安装到基板。 底部填充材料位于基底和模具之间。 使用台面将底部填充材料定位到多个区域中。 每个触点位于相应的一个空腔中。 在一些实施例中，衬底还包括互连空腔的多个通道。 在一些实施例中，衬底还包括用于进一步定位底部填充材料的多个腔内台面。 在一些实施例中，第一模具的外边缘位于位于第一空腔的边缘上的第一台面上。

公开(公告)号：US20160163650A1

公开(公告)日：2016-06-09

申请号：US14704714

申请日：2015-05-05

Applicant: Invensas Corporation

Inventor： Guilian GAO ,  Cyprian Emeka UZOH ,  Charles G. WOYCHIK ,  Hong SHEN ,  Arkalgud R. SITARAM ,  Liang WANG ,  Akash AGRAWAL ,  Rajesh KATKAR

IPC: H01L23/538 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48105 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract translation: 模具（110）和/或未开封的晶片和/或多芯片模块（MCM）被附接在插入器（120）或一些其它结构（例如另一集成电路）的顶部上并被密封剂（160）覆盖。 然后插入器从下面变薄。 在封装之前，在封装周围的插入件周围形成比密封剂更刚性的层（410），以通过机械工艺（例如CMP）来减小或消除插入件在裸片间的凹陷。 还提供其他功能。

公开(公告)号：US20150364538A1

公开(公告)日：2015-12-17

申请号：US14304535

申请日：2014-06-13

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/90 ,  H01L28/92 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15153 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In one embodiment, a method for making a 3D Metal-Insulator-Metal (MIM) capacitor includes providing a substrate having a surface, forming an array of upstanding rods or ridges on the surface, depositing a first layer of an electroconductor on the surface and the array of rods or ridges, coating the first electroconductive layer with a layer of a dielectric, and depositing a second layer of an electroconductor on the dielectric layer. In some embodiments, the array of rods or ridges can be made of a photoresist material, and in others, can comprise bonded wires.

Abstract translation: 在一个实施例中，制造3D金属 - 绝缘体 - 金属（MIM）电容器的方法包括提供具有表面的基板，在表面上形成直立杆或脊的阵列，在表面上沉积第一层电导体， 所述棒或脊的阵列，用电介质层涂覆所述第一导电层，以及在所述电介质层上沉积第二层电导体。 在一些实施例中，杆或脊的阵列可以由光致抗蚀剂材料制成，并且在另一些实施例中，可以包括接合线。

公开(公告)号：US20150262972A1

公开(公告)日：2015-09-17

申请号：US14288064

申请日：2014-05-27

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Laura Wills MIRKARIMI ,  Arkalgud SITARAM ,  Charles G. WOYCHIK

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/31 ,  H01L23/04 ,  H01L21/78 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L21/78 ,  H01L21/784 ,  H01L22/32 ,  H01L23/04 ,  H01L23/10 ,  H01L23/147 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1615 ,  H01L2924/16152 ,  H01L2924/16153 ,  H01L2924/16176 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/164 ,  H01L2924/167 ,  H01L2924/16788 ,  H01L2924/1679 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An assembly with modules (110, 1310) containing integrated circuits and attached to a wiring substrate (120) is reinforced by one or more reinforcement frames (410) attached to the wiring substrate. The modules are located in openings (e.g. cavities and/or through-holes 414) in the reinforcement frame. Other features are also provided.

Abstract translation: 包含集成电路并附接到布线基板（120）的模块（110,1310）的组件由附接到布线基板的一个或多个加强框架（410）加强。 模块位于加强框架中的开口（例如空腔和/或通孔414）中。 还提供其他功能。

公开(公告)号：US20160322326A1

公开(公告)日：2016-11-03

申请号：US14701049

申请日：2015-04-30

Applicant: INVENSAS CORPORATION

Inventor： Rajesh KATKAR ,  Tu Tam VU ,  Bongsub LEE ,  Kyong-Mo BANG ,  Xuan LI ,  Long HUYNH ,  Gabriel Z. GUEVARA ,  Akash AGRAWAL ,  Willmar SUBIDO ,  Laura Wills MIRKARIMI

IPC: H01L23/00 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L24/49 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L24/85 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/4801 ,  H01L2224/48235 ,  H01L2224/484 ,  H01L2224/4845 ,  H01L2224/49171 ,  H01L2224/49173 ,  H01L2224/49177 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/85005 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/2064 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: An apparatus relates generally to a microelectronic package. In such an apparatus, a microelectronic die has a first surface, a second surface opposite the first surface, and a sidewall surface between the first and second surfaces. A plurality of wire bond wires with proximal ends thereof are coupled to either the first surface or the second surface of the microelectronic die with distal ends of the plurality of wire bond wires extending away from either the first surface or the second surface, respectively, of the microelectronic die. A portion of the plurality of wire bond wires extends outside a perimeter of the microelectronic die into a fan-out (“FO”) region. A molding material covers the first surface, the sidewall surface, and portions of the plurality of the wire bond wires from the first surface of the microelectronic die to an outer surface of the molding material.

Abstract translation: 一种装置一般涉及微电子封装。 在这种装置中，微电子管芯具有第一表面，与第一表面相对的第二表面和第一表面和第二表面之间的侧壁表面。 多个具有近端的引线接合线被耦合到微电子管芯的第一表面或第二表面，多个引线接合线的远端分别远离第一表面或第二表面 微电子模具。 多个引线接合线的一部分在微电子管芯的周边外延伸到扇出（“FO”）区域中。 成型材料覆盖第一表面，侧壁表面以及多个引线接合线从微电子管芯的第一表面到模制材料的外表面的部分。

公开(公告)号：US20160079093A1

公开(公告)日：2016-03-17

申请号：US14488187

申请日：2014-09-16

Applicant: Invensas Corporation

Inventor： Eric S. TOSAYA ,  Rajesh KATKAR ,  Liang WANG ,  Cyprian Emeka UZOH

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/13 ,  H01L23/3178 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/06102 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/16237 ,  H01L2224/2908 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29388 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81203 ,  H01L2224/81395 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83385 ,  H01L2224/83856 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/14 ,  H01L2924/15159 ,  H01L2924/014 ,  H01L2224/81 ,  H01L2224/83

Abstract: A microelectronic component (110, 120) has a contact pad (110C, 120C, 920C) recessed in a cavity (410) and covered by underfill tape (130). The cavity has a void (410V) below the underfill tape. A protruding contact pad of another microelectronic component ruptures the underfill tape to enter the cavity and bond to the recessed contact pad. The void helps in rupturing the underfill tape, thus reducing the amount of underfill residue between the two contact pads and improving the contact resistance. Also provided is a microelectronic component having a substrate with a cavity and having a through-substrate via extending into the cavity. Other features are also provided.

Abstract translation: 微电子部件（110,120）具有凹陷在空腔（410）中并被底部填充带（130）覆盖的接触垫（110C，120C，920C）。 空腔在底部填充带下方具有空隙（410V）。 另一微电子元件的突出的接触垫破坏了底部填充带进入腔并结合到凹陷接触垫。 该空隙有助于破裂底部填充带，从而减少两个接触垫之间的底部填充残余物的量并改善接触电阻。 还提供了一种微电子部件，其具有带有空腔的基板，并且具有延伸到空腔中的贯穿基板。 还提供其他功能。

公开(公告)号：US20160071818A1

公开(公告)日：2016-03-10

申请号：US14809036

申请日：2015-07-24

Applicant: Invensas Corporation

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L25/18 ,  B81B7/00 ,  H01L23/31 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  B81C1/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/09 ,  B81B7/008 ,  B81B2207/07 ,  B81C1/0023 ,  H01L21/565 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3157 ,  H01L23/34 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/17 ,  H01L24/19 ,  H01L24/20 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/89 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/10 ,  H01L25/105 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/09181 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/33517 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/80001 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92133 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/15192 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/3511 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/32225 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

Abstract translation: 在多芯片模块（MCM）中，“超级”芯片（110N）被连接到多个“普通”芯片（110F“超”和“平原”芯片可以是任何芯片）。 超级芯片位于布线板（WB）上方，但位于平面芯片（110F）的至少一些之上。 普通芯片与超级芯片重叠。 此外，普通芯片的低速IO可以通过诸如接合线（例如BVA）或焊料堆的长直接连接连接到WB; 这种连接可以与超级芯片并排放置。 这种连接可能很长，所以超级芯片不需要很薄。 此外，如果省略通孔基板通孔（TSV），则制造成品率高，制造成本低。 提供了组合短和长直接连接以获得所需物理和电性能的其它结构。

公开(公告)号：US20180124927A1

公开(公告)日：2018-05-03

申请号：US15858791

申请日：2017-12-29

Applicant: INVENSAS CORPORATION

Inventor： Liang WANG ,  Rajesh KATKAR ,  Hong SHEN ,  Cyprian Emeka UZOH

IPC: H05K3/40 ,  H01L23/00 ,  H05K1/11 ,  H05K3/34

Abstract: A contact pad includes a solder-wettable porous network (310) which wicks the molten solder (130) and thus restricts the lateral spread of the solder, thus preventing solder bridging between adjacent contact pads.

公开(公告)号：US20160172268A1

公开(公告)日：2016-06-16

申请号：US14567918

申请日：2014-12-11

Applicant: Invensas Corporation

Inventor： Rajesh KATKAR ,  Guilian Gao ,  Charles G. Woychik ,  Wael Zohni

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/538

CPC classification number: H01L23/3677 ,  H01L21/76885 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/5384 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/00012

Abstract: In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.

Abstract translation: 在微电子器件中，衬底具有第一上表面和下表面。 集成电路管芯具有第二上表面和下表面。 互连件将基板的第一上表面耦合到集成电路管芯的第二下表面，以在它们之间进行电连接。 通孔阵列具有耦合到第二上表面的电线的近端，用于将热量从集成电路管芯导出。 模制材料设置在通孔阵列中，通孔阵列的导线的远端至少延伸到模制材料的上表面。