公开(公告)号：USD307153S

公开(公告)日：1990-04-10

申请号：US40150

申请日：1987-04-20

申请人： Dale W. Martin

设计人： Dale W. Martin

公开(公告)号：US08679863B2

公开(公告)日：2014-03-25

申请号：US13420637

申请日：2012-03-15

申请人： Jeffrey P. Gambino ,  Derrick Liu ,  Dale W. Martin ,  Gerd Pfeiffer

发明人： Jeffrey P. Gambino ,  Derrick Liu ,  Dale W. Martin ,  Gerd Pfeiffer

IPC分类号： H01L21/00

CPC分类号： H01L22/14 ,  H01L21/324 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods are provided for fine tuning substrate resistivity. The method includes measuring a resistivity of a substrate after an annealing process, and fine tuning a subsequent annealing process to achieve a target resistivity of the substrate. The fine tuning is based on the measured resistivity.

摘要翻译： 提供了微调衬底电阻率的方法。 该方法包括测量退火处理之后的衬底的电阻率，并且微调随后的退火工艺以实现衬底的目标电阻率。 微调基于测量的电阻率。

公开(公告)号：US06610607B1

公开(公告)日：2003-08-26

申请号：US09578362

申请日：2000-05-25

申请人： Douglas S. Armbrust ,  Dale W. Martin ,  Jed H. Rankin ,  Sylvia Tousley

发明人： Douglas S. Armbrust ,  Dale W. Martin ,  Jed H. Rankin ,  Sylvia Tousley

IPC分类号： H01L21461

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123

摘要： A method to define and tailor process limited lithographic features is provided. The method may be used to form sub lithographic spaces between features on a semiconductor wafer. A mask is formed and patterned on the wafer. Spacers are formed on sidewalls of the mask. The pattern of the mask and spacers is then transferred to an underlying layer.

摘要翻译： 提供了一种定义和定制加工限制光刻特征的方法。 该方法可用于在半导体晶片上的特征之间形成次光刻空间。 在晶片上形成并图案化掩模。 垫片形成在面罩的侧壁上。 然后将掩模和间隔物的图案转移到下层。

公开(公告)号：US06258673B1

公开(公告)日：2001-07-10

申请号：US09470460

申请日：1999-12-22

申请人： Kevin M. Houlihan ,  Liang-Kai Han ,  Dale W. Martin

发明人： Kevin M. Houlihan ,  Liang-Kai Han ,  Dale W. Martin

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： A method of forming an integrated circuit having four thicknesses of gate oxide in four sets of active areas by: oxidizing the silicon substrate to form an initial oxide having a thickness appropriate for a desired threshold voltage transistor; depositing a blocking mask to leave a first and fourth set of active areas exposed; implanting the first and fourth set of active areas with a dose of growth-altering ions, thereby making the first set of active areas more or less resistant to oxidation and simultaneously making the fourth set of active areas susceptible to accelerated oxidation; stripping the blocking mask; forming a second blocking mask to leave the first and second sets of active areas exposed; stripping the initial oxide in exposed active areas; stripping the second blocking mask; surface cleaning the wafer; and oxidizing the substrate in a second oxidation step such that a standard oxide thickness is formed in the second set of active areas, whereby an oxide thickness of more or less than the standard oxide thickness is formed in the first set of active areas, an oxide thickness of greater than the standard oxide thickness is formed in the third set of active areas, and a fourth oxide thickness greater than the third oxide thickness is formed in the fourth set of active areas.

摘要翻译： 一种通过以下步骤形成具有四组有源区的四种厚度的栅极氧化物的集成电路的方法：氧化硅衬底以形成具有适合于期望阈值电压晶体管的厚度的初始氧化物; 沉积阻挡掩模以留下暴露的第一和第四组有效区域; 用一定剂量的生长变化的离子注入第一组和第四组活性区域，从而使第一组活性区域或多或少抵抗氧化，同时使第四组活性区域易于加速氧化; 剥离阻挡面具; 形成第二阻挡掩模以使第一和第二组有效区域暴露; 剥离暴露的活性区域中的初始氧化物; 剥离第二阻挡面具; 表面清洗晶圆; 以及在第二氧化步骤中氧化所述衬底，使得在所述第二组有源区中形成标准氧化物厚度，由此在所述第一组有源区中形成大于或小于标准氧化物厚度的氧化物厚度， 在第三组有源区中形成大于标准氧化物厚度的厚度，并且在第四组有源区中形成大于第三氧化物厚度的第四氧化物厚度。

公开(公告)号：US20130105981A1

公开(公告)日：2013-05-02

申请号：US13285443

申请日：2011-10-31

申请人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Edward C. Cooney, III ,  James S. Dunn ,  Dale W. Martin ,  Charles F. Musante ,  BethAnn Rainey ,  Leathen Shi ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L23/48 ,  H01L21/58

CPC分类号： H01L23/4825 ,  H01L21/6835 ,  H01L21/76819 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5223 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/81 ,  H01L29/1054 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05687 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/131 ,  H01L2224/73251 ,  H01L2224/80011 ,  H01L2224/80013 ,  H01L2224/80075 ,  H01L2224/80203 ,  H01L2224/804 ,  H01L2224/80487 ,  H01L2224/80896 ,  H01L2224/80907 ,  H01L2224/80948 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/15788 ,  H01L2924/014 ,  H01L2224/08 ,  H01L2224/16 ,  H01L2924/05432 ,  H01L2924/053 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/00 ,  H01L2224/05552

摘要： Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.

摘要翻译： 用于粘结衬底表面，键合衬底组件和用于键合衬底组件的设计结构的方法。 使用器件基板的第一表面形成产品芯片的器件结构。 在产品芯片上形成用于器件结构的互连结构的布线层。 布线层被平坦化。 临时处理晶片可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层，与第一表面相对的器件基板的第二表面被结合到最终的手柄基板。 然后将临时手柄晶片从组件中取出。

公开(公告)号：US20070194385A1

公开(公告)日：2007-08-23

申请号：US11463039

申请日：2006-08-08

申请人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

发明人： Dale W. Martin ,  Steven M. Shank ,  Michael C. Triplett ,  Deborah A. Tucker

IPC分类号： H01L29/94

CPC分类号： H01L21/28247 ,  H01L21/28035 ,  H01L29/4916 ,  Y10S257/90

摘要： A gate stack structure. The structure includes (a) a semiconductor region and (b) a gate stack on top of the semiconductor region. The gate stack includes (i) a gate dielectric region on top of the semiconductor region, (ii) a first gate polysilicon region on top of the gate dielectric region, and (iii) a second gate polysilicon region on top of the first gate polysilicon region and doped with a type of dopants. The structure further includes (c) a diffusion barrier region and a spacer oxide region on a side wall of the gate stack. The diffusion barrier region (i) is sandwiched between the gate stack and the spacer oxide region and (ii) is in direct physical contact with both the first and second gate polysilicon regions, and (iii) comprises a material having a property of preventing a diffusion of oxygen-containing materials through the diffusion barrier region.

摘要翻译： 门堆栈结构。 该结构包括（a）半导体区域和（b）在半导体区域的顶部上的栅极堆叠。 栅极堆叠包括（i）在半导体区域的顶部上的栅极电介质区域，（ii）位于栅极电介质区域顶部的第一栅极多晶硅区域，以及（iii）位于第一栅极多晶硅顶部的第二栅极多晶硅区域 并掺杂一种掺杂剂。 该结构还包括（c）栅叠层的侧壁上的扩散阻挡区和间隔氧化物区。 扩散阻挡区域（i）夹在栅极叠层和间隔氧化物区域之间，（ii）与第一和第二栅极多晶硅区域直接物理接触，并且（iii）包括具有防止 含氧材料通过扩散阻挡区扩散。

公开(公告)号：US07190007B2

公开(公告)日：2007-03-13

申请号：US10710821

申请日：2004-08-05

申请人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

发明人： Matthew J. Breitwisch ,  Chung H. Lam ,  Randy W. Mann ,  Dale W. Martin

IPC分类号： H01L29/47

CPC分类号： H01L21/764 ,  H01L21/76283 ,  H01L21/76289 ,  H01L29/78654

摘要： The present invention provides a method of forming an ultra-thin and uniform layer of Si including the steps of providing a substrate having semiconducting regions separated by insulating regions; implanting dopants into the substrate to provide an etch differential doped portion in the semiconducting regions underlying an upper Si-containing surface of the semiconducting regions; forming a trench in the substrate including the semiconducting regions and the insulating regions; removing the etch differential doped portion from the semiconductor regions to produce a cavity underlying the upper surface of the semiconducting regions; and filling the trench with a trench dielectric, wherein the trench dielectric material encloses the cavity underlying the upper Si-containing surface of the semiconducting regions. The upper Si-containing surface of the semiconducting regions has a uniform thickness of less than about 100 Å.

摘要翻译： 本发明提供一种形成超薄且均匀的Si层的方法，包括以下步骤：提供具有由绝缘区分隔开的半导体区域的衬底; 将掺杂剂注入衬底中以在半导体区域的上部含Si表面下方的半导体区域中提供蚀刻差分掺杂部分; 在包括半导体区域和绝缘区域的衬底中形成沟槽; 从所述半导体区域去除所述蚀刻差分掺杂部分以在所述半导体区域的上表面下方形成空腔; 以及用沟槽电介质填充所述沟槽，其中所述沟槽电介质材料包围在所述半导体区域的所述上部含Si表面之下的空腔。 半导体区域的上部含Si表面具有小于约的均匀厚度。

公开(公告)号：US06294429B1

公开(公告)日：2001-09-25

申请号：US09448157

申请日：1999-11-24

申请人： Chung H. Lam ,  Dale W. Martin ,  Christa R. Willets

发明人： Chung H. Lam ,  Dale W. Martin ,  Christa R. Willets

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/28273 ,  H01L29/42368 ,  H01L29/42376

摘要： The present invention relates to a method of forming a charge injection region on a floating gate of a memory cell using an etching process. The present invention defines the sharp corners for electron charge injection region of a floating gate by etching the shape into the floating gate silicon rather than forming the injection point using an oxidation process. By using the etching process of the present invention, limitations on the size of the floating gate are overcome and the memory cell can be formed using the minimum geometry allowed by lithography. This allows further scaling of the cell film thickness than is presently capable and does not limit the choice of insulator film materials.

摘要翻译： 本发明涉及使用蚀刻工艺在存储单元的浮动栅极上形成电荷注入区域的方法。 本发明通过将形状蚀刻到浮动栅极硅中而不是使用氧化工艺形成注入点来限定浮动栅极的电子电荷注入区域的尖角。 通过使用本发明的蚀刻工艺，克服了对浮栅的尺寸的限制，并且可以使用光刻所允许的最小几何形状来形成存储单元。 这允许细胞膜厚度比当前能够进一步缩放，并且不限制绝缘膜材料的选择。

公开(公告)号：US06197632B1

公开(公告)日：2001-03-06

申请号：US09440776

申请日：1999-11-16

申请人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

发明人： Gary B. Bronner ,  Rama Divakaruni ,  Scott Halle ,  Dale W. Martin ,  Rajesh Rengarajan ,  Mary E. Weybright

IPC分类号： H01L218242

CPC分类号： H01L27/10894 ,  H01L27/10873 ,  H01L29/6659

摘要： This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips. An IC fabrication is provided, according to an aspect of the invention, including a silicon wafer, a DRAM array fabrication disposed on said silicon wafer having a first multitude of gate sidewall oxides, and a logic support device fabrication disposed on said wafer adjacent said DRAM array fabrication and having a second multitude of gate sidewall oxides, said first multitude of gate sidewall oxides being substantially thicker than said second multitude of gate sidewall oxides. Methods of making IC fabrications according to the invention are also provided.

摘要翻译： 本发明涉及集成电路产品和工艺。 更具体地，本发明涉及高性能动态随机存取存储器（DRAM）芯片和用于制造这种芯片的过程。 提供根据本发明的一个方面的IC制造，包括硅晶片，设置在具有第一多个栅极侧壁氧化物的所述硅晶片上的DRAM阵列制造，以及设置在与所述DRAM相邻的所述晶片上的逻辑支持器件制造 阵列制造并具有第二多个栅极侧壁氧化物，所述第一多个栅极侧壁氧化物基本上比所述第二多个栅极侧壁氧化物厚。 还提供了制造根据本发明的IC制造的方法。

公开(公告)号：US5972765A

公开(公告)日：1999-10-26

申请号：US895049

申请日：1997-07-16

申请人： William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

发明人： William F. Clark ,  Thomas G. Ference ,  Terence B. Hook ,  Dale W. Martin

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/30 ,  H01L21/316 ,  H01L21/318 ,  H01L21/324 ,  H01L21/336

CPC分类号： H01L21/28211 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/28052 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/3003 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/324 ,  H01L21/76832 ,  H01L21/76834 ,  H01L29/665 ,  H01L29/66575

摘要： Method of forming a film for a semiconductor device in which a source material comprising a deuterated species is provided during formation of the film.

摘要翻译： 形成半导体器件的膜的方法，其中在形成膜期间提供包含氘化物质的源材料。