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    Semiconductor device and methods of forming the same
    11.
    发明授权
    Semiconductor device and methods of forming the same 有权
    半导体器件及其形成方法

    公开(公告)号：US07807571B2

    公开(公告)日：2010-10-05

    申请号：US11892089

    申请日：2007-08-20

    申请人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    发明人： Kyung-In Choi ,  Gil-Heyun Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    IPC分类号： H01L21/44 ,  H01L23/52

    CPC分类号： H01L21/76868 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An example embodiment provides a method of forming a conductive pattern in a semiconductor device. The method includes forming one or more dielectric layers over a first conductive pattern formed on a substrate; forming an opening in the one or more dielectric layers to expose a portion of the first conductive pattern, forming a growth promoting layer over the exposed portion of the first conductive pattern and the one or more dielectric layers, forming a growth inhibiting layer over a portion of the growth promoting layer, and forming the second conductive layer in the opening.

    摘要翻译： 示例性实施例提供了在半导体器件中形成导电图案的方法。 该方法包括在形成在衬底上的第一导电图案上形成一个或多个电介质层; 在所述一个或多个电介质层中形成开口以暴露所述第一导电图案的一部分，在所述第一导电图案和所述一个或多个介电层的暴露部分上形成增长促进层，在所述第一导电图案的一部分上形成生长抑制层 的生长促进层，并且在开口中形成第二导电层。

    Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices
    12.
    发明申请
    Methods of Fabricating Semiconductor Devices Having Conductive Wirings and Related Flash Memory Devices 审中-公开
    制造具有导电布线和相关闪存设备的半导体器件的方法

    公开(公告)号：US20100237504A1

    公开(公告)日：2010-09-23

    申请号：US12789982

    申请日：2010-05-28

    申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L27/115 ,  H01J2237/0812 ,  H01L27/11521 ,  H01L27/11524

    摘要： A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

    摘要翻译： 在半导体衬底上设置有半导体衬底和多个下导电结构的半导体器件用导电布线。 提供了使多个下导电结构彼此电绝缘的绝缘层。 在绝缘层上设置第一绝缘夹层图案。 第一绝缘层间图案包括通过绝缘层接触衬底的接触插塞。 在接触插塞和第一绝缘层间图案上设置有蚀刻停止层。 在蚀刻停止层上设置第二绝缘层间图案。 第二绝缘层间图案包括电连接到接触插塞的导线。 还提供了相关方法和闪存设备。

    SEMICONDUCTOR DEVICES HAVING METAL INTERCONNECTIONS, SEMICONDUCTOR CLUSTER TOOLS USED IN FABRICATION THEREOF AND METHODS OF FABRICATING THE SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICES HAVING METAL INTERCONNECTIONS, SEMICONDUCTOR CLUSTER TOOLS USED IN FABRICATION THEREOF AND METHODS OF FABRICATING THE SAME 审中-公开
    具有金属互连的半导体器件，其制造中使用的半导体器件工具及其制造方法

    公开(公告)号：US20080174021A1

    公开(公告)日：2008-07-24

    申请号：US12014458

    申请日：2008-01-15

    申请人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

    发明人： Kyung-In Choi ,  Hyun-Bae Lee ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Jong-Won Hong

    IPC分类号： H01L23/52 ,  H01L21/4763 ,  C23C16/00

    CPC分类号： H01L21/76843 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating a semiconductor device is provided. The method includes providing a semiconductor substrate having a conductive pattern and forming an insulating layer on the conductive pattern and the semiconductor substrate. The insulating layer is patterned to form an opening which exposes a portion of the conductive pattern. A preliminary diffusion barrier layer is formed on an inner wall of the opening and a top surface of the insulating layer. Oxygen atoms are supplied onto the preliminary diffusion barrier layer to form a first diffusion barrier layer. A metal layer is formed on the first diffusion barrier layer. The metal layer is formed to fill the opening surrounded by the first diffusion barrier layer. A semiconductor device fabricated by the method and a semiconductor cluster tool used in fabrication of the semiconductor device are also provided.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供具有导电图案的半导体衬底和在导电图案和半导体衬底上形成绝缘层。 图案化绝缘层以形成露出导电图案的一部分的开口。 在开口的内壁和绝缘层的上表面上形成预扩散阻挡层。 将氧原子提供到预扩散阻挡层上以形成第一扩散阻挡层。 金属层形成在第一扩散阻挡层上。 金属层形成为填充由第一扩散阻挡层包围的开口。 还提供了通过该方法制造的半导体器件和用于制造半导体器件的半导体簇工具。

    Conductive Wiring for Semiconductor Devices
    15.
    发明申请
    Conductive Wiring for Semiconductor Devices 审中-公开
    半导体器件的导电布线

    公开(公告)号：US20080122076A1

    公开(公告)日：2008-05-29

    申请号：US11943166

    申请日：2007-11-20

    申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Hyun Park ,  Kyung-In Choi ,  Hyun-Bae Lee

    IPC分类号： H01L23/48

    CPC分类号： H01L27/115 ,  H01J2237/0812 ,  H01L27/11521 ,  H01L27/11524

    摘要： A conductive wiring for a semiconductor device is provided including a semiconductor substrate and a plurality of lower conductive structures on the semiconductor substrate. An insulating layer is provided that electrically insulates the plurality of lower conductive structures from one another. A first insulation interlayer pattern is provided on the insulation layer. The first insulation interlayer pattern includes a contact plug that contacts the substrate through the insulation layer. An etch-stop layer is provided on the contact plug and the first insulation interlayer pattern. A second insulation interlayer pattern is provided on the etch-stop layer. The second insulation interlayer pattern includes a conductive line that is electrically connected to the contact plug. Related methods and flash memory devices are also provided.

    摘要翻译： 在半导体衬底上设置有半导体衬底和多个下导电结构的半导体器件用导电布线。 提供了使多个下导电结构彼此电绝缘的绝缘层。 在绝缘层上设置第一绝缘夹层图案。 第一绝缘层间图案包括通过绝缘层接触衬底的接触插塞。 在接触插塞和第一绝缘层间图案上设置有蚀刻停止层。 在蚀刻停止层上设置第二绝缘层间图案。 第二绝缘层间图案包括电连接到接触插塞的导线。 还提供了相关方法和闪存设备。

    Methods of forming metal interconnection structures
    16.
    发明授权
    Methods of forming metal interconnection structures 有权
    形成金属互连结构的方法

    公开(公告)号：US08124524B2

    公开(公告)日：2012-02-28

    申请号：US12711812

    申请日：2010-02-24

    申请人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    发明人： Kyung-In Choi ,  Sang-Woo Lee ,  Jong-Myeong Lee ,  Jong-Won Hong ,  Hyun-Bae Lee

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L21/76846 ,  H01L21/76858 ,  H01L23/53223 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming a metal interconnection structure are provided. The methods include forming an insulating layer on a semiconductor substrate including a first metal interconnection. The insulating layer is patterned to form an opening that exposes the first metal interconnection. A first diffusion barrier layer is formed on the exposed first metal interconnection. After forming the first diffusion barrier layer, a second diffusion barrier layer is formed on the first diffusion barrier layer in the opening, the second diffusion barrier layer contacting a sidewall of the opening. A second metal interconnection is formed on the second diffusion barrier layer.

    摘要翻译： 提供形成金属互连结构的方法。 所述方法包括在包括第一金属互连的半导体衬底上形成绝缘层。 图案化绝缘层以形成露出第一金属互连的开口。 在暴露的第一金属互连上形成第一扩散阻挡层。 在形成第一扩散阻挡层之后，在开口中的第一扩散阻挡层上形成第二扩散阻挡层，第二扩散阻挡层与开口的侧壁接触。 第二金属互连形成在第二扩散阻挡层上。

    Method of manufacturing a semiconductor device
    17.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US07972941B2

    公开(公告)日：2011-07-05

    申请号：US12165805

    申请日：2008-07-01

    申请人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

    发明人： Jong-Won Hong ,  Gil-Heyun Choi ,  Jong-Myeong Lee ,  Geum-Jung Seong

    IPC分类号： H01L21/322

    CPC分类号： H01L21/28176 ,  H01L21/76826 ,  H01L27/10855 ,  H01L27/11521

    摘要： A gate structure is formed on a substrate. An insulating interlayer is formed covering the gate structure. The substrate is heat treated while exposing a surface of the insulating interlayer to a hydrogen gas atmosphere. A silicon nitride layer is formed directly on the interlayer insulating layer after the heat treatment and a metal wiring is formed on the insulating interlayer. The metal wiring may include copper. Heat treating the substrate while exposing a surface of the interlayer insulating layer to a hydrogen gas atmosphere may be preceded by forming a plug through the first insulating interlayer that contacts the substrate, and the metal wiring may be electrically connected to the plug. The plug may include tungsten.

    摘要翻译： 在基板上形成栅极结构。 形成覆盖栅极结构的绝缘中间层。 在将绝缘中间层的表面暴露于氢气气氛的同时对基板进行热处理。 在热处理之后，在层间绝缘层上直接形成氮化硅层，在绝缘中间层上形成金属配线。 金属布线可以包括铜。 在将层间绝缘层的表面暴露于氢气气氛的同时对基板进行热处理之前，可以通过与基板接触的第一绝缘中间层形成插塞，并且金属布线可以电连接到插头。 插头可以包括钨。

    Methods for forming aluminum metal wirings
    19.
    发明授权
    Methods for forming aluminum metal wirings 有权
    铝金属布线形成方法

    公开(公告)号：US06673718B1

    公开(公告)日：2004-01-06

    申请号：US10305244

    申请日：2002-11-27

    申请人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

    发明人： Jong-Myeong Lee ,  In-Sun Park ,  Hyeon-Deok Lee ,  Jong-Sik Chun

    IPC分类号： H01L2144

    CPC分类号： H01L21/76843 ,  H01L21/76856 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76882 ,  H01L2221/1089

    摘要： An aluminum wiring is selectively formed within a contact hole or groove of a substrate. An intermediate layer which includes nitrogen is formed over the main surface of a substrate and over the interior surface of the contact hole or groove. A first surface portion of the intermediate layer which is located over the main surface of the substrate is treated with a plasma to form a passivity layer at the first surface portion of the intermediate layer. Then, without an intervening vacuum break, an aluminum film is CAD deposited only over a second surface portion of the intermediate layer which is located over the interior surface of the contact hole or recess. The plasma treatment of the first surface portion of the intermediate layer prevents the CAD deposition of the aluminum film over the first surface portion of the intermediate layer.

    摘要翻译： 在基板的接触孔或凹槽内选择性地形成铝布线。 包含氮的中间层形成在基板的主表面上并在接触孔或凹槽的内表面上方。 用等离子体处理位于基板的主表面上方的中间层的第一表面部分，以在中间层的第一表面部分处形成被动层。 然后，没有中间真空断裂，铝膜仅沉积在中间层的位于接触孔或凹槽的内表面上方的第二表面部分上。 中间层的第一表面部分的等离子体处理防止铝膜在中间层的第一表面部分上的CAD沉积。

    Method of forming a contact in a semiconductor device
    20.
    发明授权
    Method of forming a contact in a semiconductor device 失效
    在半导体器件中形成接触的方法

    公开(公告)号：US06905960B2

    公开(公告)日：2005-06-14

    申请号：US10657140

    申请日：2003-09-09

    申请人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

    发明人： Hong-Mi Park ,  Jong-Sik Chun ,  Hyeon-Deok Lee ,  In-Sun Park ,  Jong-Myeong Lee ,  Ju-Cheol Shin

    IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L21/44

    CPC分类号： H01L21/76877 ,  H01L21/76843 ,  H01L21/76871

    摘要： In a method of forming a contact in a semiconductor device, an insulating layer is formed on the semiconductor substrate. Then, a contact hole is formed by selectively etching the insulating layer. A barrier metal layer is deposited on side and bottom surfaces of the contact hole and on a top surface of the insulating layer to a uniform thickness. A wetting layer of an oxidation-resistive metal material is deposited on the barrier metal layer. A metal layer is formed on the wetting layer and fills the contact hole to thereby form a contact in the semiconductor device.

    摘要翻译： 在半导体器件中形成接触的方法中，在半导体衬底上形成绝缘层。 然后，通过选择性地蚀刻绝缘层形成接触孔。 阻挡金属层沉积在接触孔的侧表面和底表面上，并且在绝缘层的顶表面上沉积到均匀的厚度。 在阻挡金属层上沉积抗氧化金属材料的润湿层。 在润湿层上形成金属层，并填充接触孔，从而在半导体器件中形成接触。