公开(公告)号：US08272533B1

公开(公告)日：2012-09-25

申请号：US12831396

申请日：2010-07-07

Applicant: Anthony D'Amelia ,  Mark V. Pierson

Inventor： Anthony D'Amelia ,  Mark V. Pierson

IPC: B65H3/00

CPC classification number: A47F1/10 ,  A47F2001/103

Abstract: A device for dispensing cutlery utensils individually, having a housing containing a quantity of utensils with the housing having sides and product guides within. The front wall contains an opposing leaf escapement mechanism connected to it, to hold and singulate the utensils such that they dispense seriatim, without a user being required to physically touch or interface with any part of dispenser other than the actual desired utensil.

Abstract translation: 一种用于单独分配餐具的装置，具有容纳多个器具的壳体，所述壳体具有侧面和产品引导件。 前壁包含连接到其上的相对的叶片擒纵机构，以保持和分割器具，使得它们可以分配，而不需要用户物理地接触或与实际需要的器具以外的分配器的任何部分相接触。

公开(公告)号：US06955982B2

公开(公告)日：2005-10-18

申请号：US10715649

申请日：2003-11-18

Applicant: Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

Inventor： Miguel A. Jimarez ,  Cynthia S. Milkovich ,  Mark V. Pierson

IPC: H01R12/04 ,  B23K1/00 ,  H01L21/48 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H01R4/02 ,  H05K1/14 ,  H05K3/00 ,  H05K3/28 ,  H05K3/34 ,  H05K3/36 ,  H01L21/44 ,  B23K31/00 ,  B23K31/02 ,  B21D39/00

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/42 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05671 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/81013 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/351 ,  H05K3/0032 ,  H05K3/3436 ,  H05K2201/0379 ,  H05K2201/10977 ,  H05K2201/10992 ,  H05K2203/0415 ,  H05K2203/043 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2924/00014

Abstract: An electrical structure, and associated method of fabrication, for reducing thermally induced strain in a structure that couples a first conductive body of a first substrate to a second conductive body of a second substrate (e.g., a chip to a chip carrier; a chip carrier to a circuit card). The melting point of the first conductive body exceeds the melting point of the second conductive body. The second conductive body may include eutectic lead-tin alloy, while the first conductive body may include non-eutectic lead-tin alloy. A portion of the first conductive body is coated with, or volumetrically surrounded by, a material that is nonsolderable and nonconductive. The first and second conductive bodies are coupled mechanically and electrically by surface adhesion at an uncoated portion of the first conductive body, by application of a temperature that lies between the melting points of the first and second conductive bodies.

Abstract translation: 一种电结构和相关制造方法，用于减少将第一衬底的第一导体与第二衬底的第二导电体（例如，芯片耦合到芯片载体;芯片载体）的结构中的热诱导应变 到电路卡）。 第一导电体的熔点超过第二导电体的熔点。 第二导电体可以包括共晶铅锡合金，而第一导电体可以包括非共晶铅锡合金。 第一导电体的一部分被不可焊接和不导电的材料涂覆或体积地包围。 通过施加位于第一和第二导电体的熔点之间的温度，第一和第二导电体通过在第一导电体的未涂覆部分处的表面粘附机械和电连接。

公开(公告)号：US06922294B2

公开(公告)日：2005-07-26

申请号：US10428956

申请日：2003-05-02

Applicant: Mark V. Pierson ,  Eugen Schenfeld

Inventor： Mark V. Pierson ,  Eugen Schenfeld

IPC: H04B10/12 ,  G02B6/26 ,  G02B6/43 ,  H04B10/13 ,  H04B10/135 ,  H04B10/14 ,  G02B7/02 ,  G02B6/34

CPC classification number: G02B6/43

Abstract: An optical assembly comprising an optical cube. A first optical transmitter chip and a first optical receiver chip are mounted on one surface of the optical cube. A first continuous printed circuit board is soldered to electrical surfaces of the first optical transmitter chip and the first optical receiver chip opposite the optical cube. A second optical transmitter chip and a second optical receiver chip are mounted on an opposite surface of the optical cube. A second continuous printed circuit board is soldered to electrical surfaces of the second optical transmitter chip and the second optical receiver chip opposite the optical cube. The first optical transmitter chip is optically aligned with the second optical receiver chip through the optical cube. The second optical transmitter chip is optically aligned with the first optical receiver chip through the optical cube. The first and second printed circuit boards may be bent ninety degrees and soldered to another printed circuit board, or connected to an edge connector on another printed circuit board.

Abstract translation: 一种包括光学立方体的光学组件。 第一光发射机芯片和第一光接收芯片安装在光学立方体的一个表面上。 将第一连续印刷电路板焊接到与光学立方体相对的第一光发射器芯片和第一光接收器芯片的电表面。 第二光发射器芯片和第二光接收器芯片安装在光学立方体的相对表面上。 将第二连续印刷电路板焊接到与光学立方体相对的第二光发射器芯片和第二光接收器芯片的电表面。 第一光发射器芯片通过光学立方体与第二光接收器芯片光学对准。 第二光发射器芯片通过光学立方体与第一光接收器芯片光学对准。 第一和第二印刷电路板可以弯曲九十度并且焊接到另一个印刷电路板，或者连接到另一个印刷电路板上的边缘连接器。

公开(公告)号：US06805280B2

公开(公告)日：2004-10-19

申请号：US10041261

申请日：2002-01-08

Applicant: Lisa J. Jimarez ,  Mark V. Pierson

Inventor： Lisa J. Jimarez ,  Mark V. Pierson

IPC: B23K120

CPC classification number: H05K3/462 ,  H05K3/321 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/096

Abstract: The current invention provides a method of attaching a plurality of cores wherein a core has a via with a conductive surface to be electrically connected to a conductive surface on another core. The method provides for applying a metallurgical paste to a conductive surface, removing a portion of the flux from the paste and joining the two cores. The current invention also provides a structure including a plurality of cores wherein a metallurgical paste electrically connects a via with a conductive surface on a core to a conductive surface on another core.

Abstract translation: 本发明提供了一种附接多个芯的方法，其中芯具有导电表面的通孔以电连接到另一芯上的导电表面。 该方法提供将冶金膏施加到导电表面，从糊料中去除一部分助熔剂并连接两个芯。 本发明还提供了一种包括多个芯的结构，其中冶金膏将通孔与芯上的导电表面电连接到另一芯上的导电表面。

公开(公告)号：US06719871B2

公开(公告)日：2004-04-13

申请号：US09757185

申请日：2001-01-09

Applicant: Frank D. Egitto ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Luis J. Matienzo ,  Mark V. Pierson

Inventor： Frank D. Egitto ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Luis J. Matienzo ,  Mark V. Pierson

IPC: B32B3114

CPC classification number: B29C59/14 ,  H01L21/56 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method for bonding heat sinks to packaged electronic components comprises the steps of: (a) exposing to a plasma a surface of a molded polymer formed on a substrate; (b) allowing the plasma to at least partially convert silicon-containing residue on the surface to silica; and (c) bonding an article to the surface by applying an adherent between the article and the surface. Often, the silicon-containing residue is silicone oil, a mold release compound, which may prevent the formation of a bond when using conventional bonding methods and materials. The silica layer formed on the surface of the molded polymer assists in formation of a proper bond. The plasma may be an oxygen plasma and the adherent may be selected from either a heat cured silicone-based paste adhesive with a metal oxide filler or a heat cured porous polymer film impregnated with adhesive. In particular, the film may be polytetrafluoroethylene, the adhesive may be polybutadine, and the film may be further impregnated with a metal oxide heat transfer medium, such as zinc oxide. An alternate method comprises applying the porous polymer film without plasma treatment and heat curing the film to form a proper bond.

公开(公告)号：US06517662B2

公开(公告)日：2003-02-11

申请号：US09397739

申请日：1999-09-16

Applicant: Thomas M. Culnane ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Charles G. Woychik

Inventor： Thomas M. Culnane ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Charles G. Woychik

IPC: B29C6502

CPC classification number: H01L23/49572 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/1532

Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.

Abstract translation: 一种半导体芯片载体组件，其包括在其表面之一上具有与半导体芯片电连通的金属化路径的柔性基板。 加强件邻近所述柔性基底设置并通过粘合剂组合物与其结合。 将包含可固化粘合剂的微孔膜的粘合剂组合物设置在柔性基材和加强件之间。 盖板粘合到半导体芯片和加强件上。 还描述了将柔性基底设置在其中放置粘合剂组合物和加强件的真空固定装置中，随后施加热和压力以固化可固化粘合剂的方法。

公开(公告)号：US06344099B1

公开(公告)日：2002-02-05

申请号：US09668141

申请日：2000-09-25

Applicant: Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

Inventor： Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

IPC: B32B3100

CPC classification number: B32B38/18 ,  B32B37/12 ,  G02F1/13336 ,  Y10S345/903 ,  Y10T156/1089 ,  Y10T156/109 ,  Y10T156/1092 ,  Y10T156/1093 ,  Y10T156/1754 ,  Y10T156/1756 ,  Y10T156/1759

Abstract: A system for aligning and attaching together a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate loading station where a coverplate that the tiles are to be attached to is arranged on a coverplate support. A coverplate bonding material dispensing station where a bonding material for bonding the tiles to the coverplate is applied to a surface of the coverplate. A tile placement station where the tiles are arranged on the coverplate. A tile aligning and securing station where the tiles are aligned relative to each other and the coverplate by the tile aligner and where the tiles are at least partially bonded to the coverplate. A tile assembly bonding material dispensing station where a bonding material is applied to a surface of the tiles opposite the side that the coverplate is bonded to. A backplate placement station where a backplate is arranged on the tiles. A backplate aligning and securing station where the backplate is aligned with the tiles and the coverplate and at least partially secured to the tiles. A full bonding station where the tiles are fully bonded to the coverplate and the backplate.

Abstract translation: 一种用于对准和连接在一起的多个薄膜晶体管瓦片用于构建平板显示器的系统。 一个盖板加载站，其中瓦片要附着的盖板布置在盖板支架上。 一种覆盖板接合材料分配站，其中用于将瓦片粘合到盖板上的粘合材料施加到盖板的表面。 瓦片布置台，其中瓦片布置在盖板上。 瓦片对准和固定台，其中瓦片通过瓦片对准器相对于彼此并且盖板对准，并且瓦片至少部分地结合到盖板。 一种瓦片组合接合材料分配站，其中粘合材料施加到瓦片与盖板粘合的一侧相反的表面。 背板放置台，其中背板设置在瓦片上。 背板对准和固定台，其中背板与瓦片和盖板对齐并且至少部分地固定到瓦片。 一个完整的焊接站，其中瓦片完全结合到盖板和背板。

公开(公告)号：US5980348A

公开(公告)日：1999-11-09

申请号：US82287

申请日：1998-05-19

Applicant: Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

Inventor： Michael A. Gaynes ,  Allan O. Johnson ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Edward J. Tasillo

IPC: G02F1/1333 ,  H01J9/18

CPC classification number: G02F1/13336 ,  Y10S345/903

Abstract: A method for aligning a plurality of thin film transistor tiles for constructing a flat panel display. A coverplate is arranged on a coverplate support. A first layer of a bonding material is applied to at least one of a first side of each of the tiles and a surface of the coverplate on which the tiles are to be secured. The tiles are arranged on the coverplate, such that the first layer of bonding material is arranged between the tiles and the coverplate. The tiles are connected to an alignment apparatus. The tiles are aligned relative to each other and the coverplate. The tiles are at least partially secured to the coverplate.

公开(公告)号：US5973389A

公开(公告)日：1999-10-26

申请号：US844865

申请日：1997-04-22

Applicant: Thomas M. Culnane ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Charles G. Woychik

Inventor： Thomas M. Culnane ,  Michael A. Gaynes ,  Ramesh R. Kodnani ,  Mark V. Pierson ,  Charles G. Woychik

IPC: H01L21/60 ,  H01L23/12 ,  H01L23/495 ,  H01L23/02

CPC classification number: H01L23/49572 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/1532

Abstract: A semiconductor chip carrier assembly which includes a flexible substrate having a metallicized path on one of its surfaces in electrical communication with a semiconductor chip. A stiffener is disposed adjacent to said flexible substrate and is bonded thereto by an adhesive composition. The adhesive composition which comprises a microporous film laden with a curable adhesive is disposed between the flexible substrate and the stiffener. A cover plate is adhesively bonded to the semiconductor chip and to the stiffener. A process of making the assembly involving disposition of the flexible substrate in a vacuum fixture upon which the adhesive composition and stiffener is placed followed by the application of heat and pressure to cure the curable adhesive is also described.

Abstract translation: 一种半导体芯片载体组件，其包括在其表面之一上具有与半导体芯片电连通的金属化路径的柔性基板。 加强件邻近所述柔性基底设置并通过粘合剂组合物与其结合。 将包含可固化粘合剂的微孔膜的粘合剂组合物设置在柔性基材和加强件之间。 盖板粘合到半导体芯片和加强件上。 还描述了将柔性基底设置在其中放置粘合剂组合物和加强件的真空固定装置中，随后施加热和压力以固化可固化粘合剂的方法。

公开(公告)号：US5831828A

公开(公告)日：1998-11-03

申请号：US71630

申请日：1993-06-03

Applicant: Lawrence R. Cutting ,  Michael A. Gaynes ,  Eric A. Johnson ,  Cynthia S. Milkovich ,  Jeffrey S. Perkins ,  Mark V. Pierson ,  Steven E. Poetzinger ,  Jerzy Zalesinski

Inventor： Lawrence R. Cutting ,  Michael A. Gaynes ,  Eric A. Johnson ,  Cynthia S. Milkovich ,  Jeffrey S. Perkins ,  Mark V. Pierson ,  Steven E. Poetzinger ,  Jerzy Zalesinski

IPC: H01L21/48 ,  H01L23/367 ,  H01L23/538 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/00 ,  H05K3/12 ,  H05K3/34 ,  H05K7/20

CPC classification number: H05K7/20454 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/3672 ,  H01L23/5387 ,  H05K1/021 ,  H05K1/189 ,  H05K3/0061 ,  H05K3/1216 ,  H05K3/4691 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01322 ,  H05K1/0298 ,  H05K1/182 ,  H05K2201/0154 ,  H05K2201/09063 ,  H05K2201/096 ,  H05K2201/09745 ,  H05K2201/1056 ,  H05K2201/2009 ,  H05K2203/1394 ,  H05K3/3415 ,  H05K3/3452 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A multi-layer flexible circuit board has thicker regions to which surface-mount-technology (SMT) components (such as flip chips and QFPs) and pin-in-hole (PIH) components are mounted on both sides and which contains conductive through vias between wiring layers. After the SMT components have been mounted to the first side, a screening fixture with a support surface that has cavities conforming the components on the first side, is used to screen solder paste to the other side of the board. The thicker regions are surrounded by thinner regions of the board with fewer wiring layers and preferably fewer or thinner dielectric layers, and which can be bent along a line without bending the thicker regions. A common heat spreader plate with cavities or holes for multiple components is laminated to the thicker regions on one side of the board. The thicker regions have windows in which wire-bond chips are mounted to the heat spreader and the chips are wirebonded to the other side of the board. A thermally conductive adhesive or grease connects between the components and the bottoms of the cavities. Two heat sink plates are bolted together and along with other such heat sink plates are bolted to an enclosure frame to improve thermal performance.

Abstract translation: 多层柔性电路板具有较厚的区域，表面贴装技术（SMT）部件（例如倒装芯片和QFP）和销钉（PIH）部件安装在两侧并且包含导电通孔 布线层之间。 在SMT部件已经安装到第一侧之后，使用具有与第一面上的部件相符合的空腔的支撑表面的屏蔽夹具将焊膏屏蔽到板的另一侧。 较厚的区域由较薄的区域围绕，具有更少的布线层，优选更少或更薄的介电层，并且可以沿着线弯曲而不弯曲较厚的区域。 具有用于多个部件的空腔或孔的普通散热板被层压到板的一侧上较厚的区域。 较厚的区域具有将引线键合芯片安装到散热器的窗口，并且芯片被引线键合到板的另一侧。 导热粘合剂或油脂在部件和空腔的底部之间连接。 两个散热板被螺栓连接在一起，并且与其它这样的散热板一起用螺栓连接到外壳框架以改善热性能。