METHODS, DEVICES, AND SYSTEMS RELATED TO FORMING SEMICONDUCTOR POWER DEVICES WITH A HANDLE SUBSTRATE
    14.
    发明申请
    METHODS, DEVICES, AND SYSTEMS RELATED TO FORMING SEMICONDUCTOR POWER DEVICES WITH A HANDLE SUBSTRATE 有权
    与形成具有手柄基板的半导体电源装置相关的方法,装置和系统

    公开(公告)号:US20140239348A1

    公开(公告)日:2014-08-28

    申请号:US13774313

    申请日:2013-02-22

    Abstract: Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method of forming a semiconductor device assembly includes forming a semiconductor device assembly that includes a handle substrate, a semiconductor structure having a first side and a second side opposite the first side, and an intermediary material between the semiconductor structure and the handle substrate. The method also includes removing material from the semiconductor structure to form an opening extending from the first side of the semiconductor structure to at least the intermediary material at the second side of the semiconductor structure. The method further includes removing at least a portion of the intermediary material through the opening in the semiconductor structure to undercut the second side of the semiconductor structure.

    Abstract translation: 本文公开了制造装置组件以及相关联的半导体组件,装置,系统的方法。 在一个实施例中,形成半导体器件组件的方法包括形成半导体器件组件,其包括处理衬底,具有第一侧和与第一侧相对的第二侧的半导体结构,以及在半导体结构和 处理基板。 该方法还包括从半导体结构去除材料以形成从半导体结构的第一侧延伸到半导体结构的第二侧的至少中间材料的开口。 该方法还包括通过半导体结构中的开口去除中间材料的至少一部分,以切割半导体结构的第二侧。

    BACK-TO-BACK SOLID STATE LIGHTING DEVICES AND ASSOCIATED METHODS

    公开(公告)号:US20250140774A1

    公开(公告)日:2025-05-01

    申请号:US19011500

    申请日:2025-01-06

    Abstract: Solid state lights (SSLs) including a back-to-back solid state emitters (SSEs) and associated methods are disclosed herein. In various embodiments, an SSL can include a carrier substrate having a first surface and a second surface different from the first surface. First and second through substrate interconnects (TSIs) can extend from the first surface of the carrier substrate to the second surface. The SSL can further include a first and a second SSE, each having a front side and a back side opposite the front side. The back side of the first SSE faces the first surface of the carrier substrate and the first SSE is electrically coupled to the first and second TSIs. The back side of the second SSE faces the second surface of the carrier substrate and the second SSE is electrically coupled to the first and second TSIs.

    Devices, systems, and methods related to removing parasitic conduction in semiconductor devices
    16.
    发明授权
    Devices, systems, and methods related to removing parasitic conduction in semiconductor devices 有权
    与去除半导体器件中的寄生导通相关的器件,系统和方法

    公开(公告)号:US09577058B2

    公开(公告)日:2017-02-21

    申请号:US14796974

    申请日:2015-07-10

    Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.

    Abstract translation: 本文公开了用于制造半导体器件的半导体器件和方法。 根据特定实施例配置的方法包括从外延衬底形成半导体材料的堆叠,其中半导体材料堆叠限定异质结,并且其中半导体材料堆叠和外延衬底进一步限定包括 邻近外延衬底的半导体堆叠部分。 该方法还包括将半导体材料堆叠附接到载体,其中载体被配置为提供到异质结的信号路径。 该方法还包括通过去除外延衬底来暴露体区。

    DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES
    18.
    发明申请
    DEVICES, SYSTEMS, AND METHODS RELATED TO REMOVING PARASITIC CONDUCTION IN SEMICONDUCTOR DEVICES 有权
    与半导体器件中的移除导通相关的器件,系统和方法

    公开(公告)号:US20140097441A1

    公开(公告)日:2014-04-10

    申请号:US13646307

    申请日:2012-10-05

    Abstract: Semiconductor devices and methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming a stack of semiconductor materials from an epitaxial substrate, where the stack of semiconductor materials defines a heterojunction, and where the stack of semiconductor materials and the epitaxial substrate further define a bulk region that includes a portion of the semiconductor stack adjacent the epitaxial substrate. The method further includes attaching the stack of semiconductor materials to a carrier, where the carrier is configured to provide a signal path to the heterojunction. The method also includes exposing the bulk region by removing the epitaxial substrate.

    Abstract translation: 本文公开了用于制造半导体器件的半导体器件和方法。 根据特定实施例配置的方法包括从外延衬底形成半导体材料的堆叠,其中半导体材料堆叠限定异质结,并且其中半导体材料堆叠和外延衬底进一步限定包括 邻近外延衬底的半导体堆叠部分。 该方法还包括将半导体材料堆叠附接到载体,其中载体被配置为提供到异质结的信号路径。 该方法还包括通过去除外延衬底来暴露体区。

    METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES
    19.
    发明申请
    METHODS FOR FORMING SMALL-SCALE CAPACITOR STRUCTURES 审中-公开
    形成小尺寸电容器结构的方法

    公开(公告)号:US20130166057A1

    公开(公告)日:2013-06-27

    申请号:US13775878

    申请日:2013-02-25

    Abstract: The present disclosure provides small scale capacitors (e.g., DRAM capacitors) and methods of forming such capacitors. One exemplary implementation provides a method of fabricating a capacitor that includes sequentially forming a first electrode, a dielectric layer, and a second electrode. At least one of the electrodes may be formed by a) reacting two precursors to deposit a first conductive layer at a first deposition rate, and b) depositing a second conductive layer at a second, lower deposition rate by depositing a precursor layer of one precursor at least one monolayer thick and exposing that precursor layer to another precursor to form a nanolayer reaction product. The second conductive layer may be in contact with the dielectric layer and have a thickness of no greater than about 50 Å.

    Abstract translation: 本公开提供小尺寸电容器(例如,DRAM电容器)以及形成这种电容器的方法。 一个示例性实施例提供了一种制造电容器的方法,该电容器包括顺序地形成第一电极,电介质层和第二电极。 可以通过以下方式形成至少一个电极:a)使两个前体反应以第一沉积速率沉积第一导电层,以及b)通过沉积一个前体的前体层以第二较低沉积速率沉积第二导电层 至少一层单层,并将该前体层暴露于另一种前体以形成纳米层反应产物。 第二导电层可以与介电层接触并具有不大于约的厚度。

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