公开(公告)号：US20190363050A1

公开(公告)日：2019-11-28

申请号：US16405644

申请日：2019-05-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yosuke KATSURA ,  Shinji KATAYAMA ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

IPC: H01L23/538 ,  H05K1/02 ,  H04L25/02 ,  H01L23/66 ,  H01L23/498

Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.

公开(公告)号：US20190198463A1

公开(公告)日：2019-06-27

申请号：US16192323

申请日：2018-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Shinji KATAYAMA ,  Keita TSUCHIYA

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3185 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2224/16227

Abstract: A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.

公开(公告)号：US20180098420A1

公开(公告)日：2018-04-05

申请号：US15549107

申请日：2015-08-20

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Wataru SHIROI ,  Kenichi KUBOYAMA

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/0248 ,  H01L23/32 ,  H01L25/04 ,  H01L25/18 ,  H01L2224/16225 ,  H05K1/0239 ,  H05K1/0243 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/113 ,  H05K1/119 ,  H05K1/141 ,  H05K1/16 ,  H05K1/18 ,  H05K1/181 ,  H05K1/182 ,  H05K3/4046 ,  H05K7/02 ,  H05K2201/09218 ,  H05K2201/10378

Abstract: A semiconductor device according to an embodiment has a first semiconductor component and a second semiconductor component which are electrically connected with each other via an interposer. The interposer has a plurality of first signal wiring paths, and a plurality of second signal wiring paths each having a path distance smaller than each of the plurality of first signal wiring paths. Furthermore, the first semiconductor component includes a first electrode, a second electrode, and a third electrode arranged in order in a first direction. Furthermore, the second semiconductor component includes a fourth electrode, a fifth electrode, and a sixth electrode arranged in order in the first direction. Furthermore, the first electrode is connected with the fourth electrode via the first signal wiring path, the second electrode is connected with the fifth electrode via the first signal wiring path, and the third electrode is connected with the sixth electrode via the first signal wiring path.

公开(公告)号：US20150214142A1

公开(公告)日：2015-07-30

申请号：US14590291

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI ,  Ryuichi OIKAWA

IPC: H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16057 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K1/0225 ,  H05K1/0253 ,  H05K2201/09336 ,  H05K2201/09681 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

Abstract: To improve noise immunity of a semiconductor device. A wiring substrate of a semiconductor device includes a first wiring layer where a wire is formed to which signals are sent, and a second wiring layer that is mounted adjacent to the upper layer or the lower layer of the first wiring layer. The second wiring layer includes a conductor plane where an aperture section is formed at a position overlapped with a portion of the wire 23 in the thickness direction, and a conductor pattern that is mounted within the aperture section of the conductor plane. The conductor pattern includes a main pattern section (mesh pattern section) that is isolated from the conductor plane, and plural coupling sections that couple the main pattern section and the conductor plane.

Abstract translation: 为了提高半导体器件的抗噪声性。 半导体器件的布线基板包括形成有信号发送线的第一布线层和与第一布线层的上层或下层相邻地安装的第二布线层。 第二布线层包括在厚度方向上与导线23的一部分重叠的位置处形成开口部的导体平面和安装在导体平面的开口部内的导体图案。 导体图案包括与导体平面隔离的主图案部分（网格图案部分）和耦合主图案部分和导体平面的多个耦合部分。

公开(公告)号：US20220406700A1

公开(公告)日：2022-12-22

申请号：US17722823

申请日：2022-04-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Nobuhiro KINOSHITA ,  Shuuichi KARIYAZAKI ,  Keita TSUCHIYA

IPC: H01L23/498 ,  H01L23/66

Abstract: A wiring substrate includes: a first insulating layer; a first metal pattern formed on the first insulating layer; a second insulating layer formed on the first insulating layer so as to cover the first metal pattern; a second metal pattern formed on the second insulating layer; and an organic insulating film contacted with a portion of the second metal pattern. Also, the first metal pattern has: a first lower surface contacted with the first insulating layer; and a first upper surface contacted with the second insulating layer. Also, the second metal pattern has: a second lower surface contacted with the second insulating layer; and a second upper surface contacted with the organic insulating film. Further, a surface roughness of the second upper surface is larger than a surface roughness of each of the second lower surface, the first upper surface and the first lower surface.

公开(公告)号：US20190198462A1

公开(公告)日：2019-06-27

申请号：US16175522

申请日：2018-10-30

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuyuki NAKAGAWA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Shuuichi KARIYAZAKI ,  Norio CHUJO ,  Masayoshi YAGYU ,  Yutaka UEMATSU

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/367 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.

公开(公告)号：US20180374788A1

公开(公告)日：2018-12-27

申请号：US16063280

申请日：2016-02-10

Applicant: Renesas Electronics Corporation

Inventor： Kazuyuki NAKAGAWA ,  Katsushi TERAJIMA ,  Keita TSUCHIYA ,  Yoshiaki SATO ,  Hiroyuki UCHIDA ,  Yuji KAYASHIMA ,  Shuuichi KARIYAZAKI ,  Shinji BABA

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065

Abstract: According to an embodiment of the present invention, there is provided a semiconductor device having a first semiconductor component and a second semiconductor component which are mounted on a wiring substrate. The first semiconductor component has a first terminal for transmitting a first signal between the first semiconductor component and the outside and a second terminal for transmitting a second signal between the first semiconductor component and the second semiconductor component. In addition, the second semiconductor component has a third terminal for transmitting the second signal between the second semiconductor component and the first semiconductor component. Further, the first signal is transmitted at a higher frequency than the second signal. Furthermore, the second terminal of the first semiconductor component and the third terminal of the second semiconductor component are electrically connected to each other via the first wiring member. In addition, the first terminal of the first semiconductor component is electrically connected to the wiring substrate via a first bump electrode without the first wiring member interposed therebetween.

公开(公告)号：US20180151460A1

公开(公告)日：2018-05-31

申请号：US15879610

申请日：2018-01-25

Applicant: Renesas Electronics Corporation

Inventor： Ryuichi OIKAWA ,  Toshihiko OCHIAI ,  Shuuichi KARIYAZAKI ,  Yuji KAYASHIMA ,  Tsuyoshi KIDA

IPC: H01L23/14 ,  H01L23/498 ,  H01L25/065 ,  H01L23/66

CPC classification number: H01L23/147 ,  H01L23/00 ,  H01L23/32 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/66 ,  H01L25/065 ,  H01L25/0655 ,  H01L25/07 ,  H01L25/18 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/16225 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

公开(公告)号：US20180025998A1

公开(公告)日：2018-01-25

申请号：US15719634

申请日：2017-09-29

Applicant: Renesas Electronics Corporation

Inventor： Shuuichi KARIYAZAKI

IPC: H01L23/64 ,  H01L23/50 ,  H01L23/538 ,  H01L23/66 ,  H01L23/522 ,  H01L23/498 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/642 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/5383 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6661 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/30111 ,  H05K1/0231 ,  H05K1/181 ,  H05K2201/10378

Abstract: A semiconductor device with enhanced performance. The semiconductor device has a high speed transmission path which includes a first coupling part to couple a semiconductor chip and an interposer electrically, a second coupling part to couple the interposer and a wiring substrate, and an external terminal formed on the bottom surface of the wiring substrate. The high speed transmission path includes a first transmission part located in the interposer to couple the first and second coupling parts electrically and a second transmission part located in the wiring substrate to couple the second coupling part and the external terminal electrically. The high speed transmission path is coupled with a correction circuit in which one edge is coupled with a branching part located midway in the second transmission part and the other edge is coupled with a capacitative element, and the capacitative element is formed in the interposer.

公开(公告)号：US20150364392A1

公开(公告)日：2015-12-17

申请号：US14833341

申请日：2015-08-24

Applicant: Renesas Electronics Corporation

Inventor： Satoshi TAKAHASHI ,  Shuuichi KARIYAZAKI

IPC: H01L23/04 ,  H01L23/367 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/04 ,  H01L21/50 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/544 ,  H01L23/562 ,  H01L24/09 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/49 ,  H01L24/74 ,  H01L24/97 ,  H01L25/165 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0913 ,  H01L2224/13101 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K1/0266 ,  H05K3/3442 ,  H05K3/3489 ,  H05K2201/066 ,  H05K2201/09781 ,  H05K2201/1056 ,  H05K2201/10636 ,  H05K2203/0169 ,  H05K2203/0173 ,  H05K2203/167 ,  H05K2203/168 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/014

Abstract: An error is prevented from being generated at a mounting position of an electronic component on a wiring substrate. A first semiconductor chip has a main surface and a rear surface. The rear surface is an opposite surface of the main surface. The rear surface of the first semiconductor chip is an opposite surface of the main surface thereof. A wiring substrate is rectangular, and has a main surface and a rear surface. The first semiconductor chip is mounted on the main surface of the wiring substrate. A lid covers the main surface of the wiring substrate, and the first semiconductor chip. An electronic component is mounted on the rear surface of the wiring substrate. The main surface of the wiring substrate has uncovered regions that are not covered with the lid at at least two corners facing each other.

Abstract translation: 防止在布线基板上的电子部件的安装位置产生误差。 第一半导体芯片具有主表面和后表面。 后表面是主表面的相反表面。 第一半导体芯片的后表面是其主表面的相对表面。 布线基板是矩形的，并且具有主表面和后表面。 第一半导体芯片安装在布线基板的主表面上。 盖子覆盖布线基板的主表面和第一半导体芯片。 电子部件安装在布线基板的背面。 布线基板的主表面在至少两个彼此面对的角部处未被盖子覆盖的未覆盖区域。