公开(公告)号：US20210013176A1

公开(公告)日：2021-01-14

申请号：US16661633

申请日：2019-10-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Francis J. CARNEY ,  Chee Hiong CHEW ,  Shunsuke YASUDA

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/02

Abstract: A method includes placing a coupling mechanism material layer on a backside of a wafer having power devices fabricated on a frontside thereof, and placing conductive spacer blocks on the coupling mechanism material layer on a backside of the selected wafer. The method further includes activating the coupling mechanism material to bond the conductive spacer blocks to the backside of the selected wafer, and singulating the wafer to separate the vertical device stacks, each of the singulated vertical device stacks including a device die bonded to, or fused with, a conductive spacer block.

公开(公告)号：US20190229052A1

公开(公告)日：2019-07-25

申请号：US16374015

申请日：2019-04-03

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Yenting WEN ,  George CHANG

IPC: H01L23/528 ,  H01L23/492 ,  H01L21/50 ,  H01L23/532 ,  H01L21/304 ,  H01L23/36 ,  H01L21/78 ,  H01L23/522

Abstract: Implementations of semiconductor packages may include: a prefabricated electrically conductive section; two or more metal oxide semiconductor field effect transistors (MOSFET) physically coupled together; and a back metal coupled to the two or more MOSFETs; wherein the electrically conductive section may be coupled to the back metal and may be configured to electrically couple the two or more MOSFETs together during operation of the two or more MOSFETs.

公开(公告)号：US20190148306A1

公开(公告)日：2019-05-16

申请号：US16229186

申请日：2018-12-21

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Shinzo ISHIBE ,  Kazuyuki SUTO

IPC: H01L23/532 ,  H01L23/00 ,  H01L21/265 ,  H01L29/861 ,  H01L29/739 ,  H01L21/324 ,  H01L23/528 ,  H01L21/22 ,  H01L21/28 ,  H01L23/482 ,  H01L21/304

Abstract: Implementations of a semiconductor device may include: a silicon substrate including a first side and a second side. The second side of the substrate may include an active area. The device may include a metal stack including: a back metallization on the first side of the substrate, an electroplated metal layer on the back metallization; and an evaporated gold metal layer on the electroplated metal layer.

公开(公告)号：US20190109106A1

公开(公告)日：2019-04-11

申请号：US16214428

申请日：2018-12-10

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN

IPC: H01L23/00 ,  H01L21/324 ,  H01L21/02 ,  H01L21/304 ,  H01L21/265

Abstract: Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

公开(公告)号：US20180061791A1

公开(公告)日：2018-03-01

申请号：US15254640

申请日：2016-09-01

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN

IPC: H01L23/00 ,  H01L21/304 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L24/05 ,  H01L21/02035 ,  H01L21/26513 ,  H01L21/304 ,  H01L21/324 ,  H01L24/03 ,  H01L24/45 ,  H01L2224/0218 ,  H01L2224/0219 ,  H01L2224/02205 ,  H01L2224/02215 ,  H01L2224/03462 ,  H01L2224/0362 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05582 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/45015 ,  H01L2224/45147 ,  H01L2924/01028 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/07025 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/2076 ,  H01L2924/00014

Abstract: Implementations of semiconductor packages may include: a silicon die including a pad, the pad including aluminum and copper; a passivation layer over at least a portion of the silicon die and a layer of one of a polyimide (PI) a polybenzoxazole (PBO), or a polymer resin coupled to the passivation layer. The package may include a first copper layer coupled over the pad, the first copper layer being about 1 microns to about 20 microns thick; a second copper layer coupled over the first copper layer, the second copper layer may be about 5 microns to about 40 microns thick; where a width of the first copper layer above the pad may be wider than a width of the second copper layer above the pad. The first and second copper layers may be configured to bond with a heavy copper wire or solder with a copper clip.

公开(公告)号：US20250149449A1

公开(公告)日：2025-05-08

申请号：US19011340

申请日：2025-01-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Takashi NOMA ,  Francis J. CARNEY

IPC: H01L23/532 ,  H01L23/00

Abstract: Implementations of semiconductor packages may include a die having a first side and a second side opposite the first side, a first metal layer coupled to the first side of the die, a tin layer coupled to the first metal layer, the first metal layer between the die and the tin layer, a backside metal layer coupled to the second side of the die, and a mold compound coupled to the die. The mold compound may cover a plurality of sidewalls of the first metal layer and a plurality of sidewalls of the tin layer and a surface of the mold compound is coplanar with a surface of the tin layer.

公开(公告)号：US20250126853A1

公开(公告)日：2025-04-17

申请号：US18988822

申请日：2024-12-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Peter MOENS ,  Gordon M. GRIVNA ,  Yusheng LIN

IPC: H10D62/10 ,  H01L21/762 ,  H01L25/07 ,  H10D62/85

Abstract: In a general aspect, a method includes forming, in a semiconductor device layer disposed on a semiconductor substrate, an opening between a first semiconductor device stack included in the semiconductor device layer and a second semiconductor device stack included in the semiconductor device layer. The method also includes forming a trench in the semiconductor substrate between the first semiconductor device stack and the second semiconductor device stack, the trench corresponding with the opening. The method further includes filling the trench with a first dielectric material, thinning the semiconductor substrate to expose the first dielectric material and separate the semiconductor substrate into a first substrate portion and a second substrate portion, and forming a layer of a second dielectric material on the first substrate portion, the second substrate portion and the exposed first dielectric material.

公开(公告)号：US20240282668A1

公开(公告)日：2024-08-22

申请号：US18172904

申请日：2023-02-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yong LIU ,  Liangbiao CHEN ,  Yusheng LIN ,  Chee Hiong CHEW

IPC: H01L23/433 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/4334 ,  H01L21/4882 ,  H01L21/565 ,  H01L23/3107

Abstract: A protective dam can relieve stress in a chip assembly of a high-power semiconductor device module used in electric vehicle or industrial applications. Some chip assemblies that incorporate copper spacers for thermal dissipation can cause the device module to become vulnerable to cracking. Adding a protective dam can absorb stress to prevent damage to materials surrounding the chip assembly. Various types of protective dams are presented, including high profile flexible protective dams, low profile flexible protective dams, metallic protective dams, and integral protective dams. The protective dams can be incorporated into a high-power semiconductor device module that features single sided or dual sided cooling via direct bond metal structures.

公开(公告)号：US20240234456A1

公开(公告)日：2024-07-11

申请号：US18153267

申请日：2023-01-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yu-Te HSIEH ,  Yusheng LIN

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14618 ,  H01L27/14685

Abstract: In a general aspect, a package includes a semiconductor die including an optical device having an optically active area on a first side of the semiconductor die. The package also includes a glass cover having an antireflective coating disposed on a central portion of a first side of the glass cover. A perimeter portion of the first side of the glass cover excludes the antireflective coating. The package further includes an adhesive resin coupling the perimeter portion of the first side of the glass cover with the first side of the semiconductor die, such that the glass cover is disposed above and spaced from the optically active area.

公开(公告)号：US20240145515A1

公开(公告)日：2024-05-02

申请号：US18558593

申请日：2022-04-27

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Swarnal BORTHAKUR ,  Mario M. PELELLA ,  Chandrasekharan KOTHANDARAMAN ,  Marc Allen SULFRIDGE ,  Yusheng LIN ,  Larry Duane KINSMAN

IPC: H01L27/146 ,  H01L23/00

CPC classification number: H01L27/14634 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/19 ,  H01L24/20 ,  H01L24/94 ,  H01L24/96 ,  H01L27/14636 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L2224/19 ,  H01L2224/211 ,  H01L2224/32225 ,  H01L2224/80357 ,  H01L2224/80379 ,  H01L2224/80896 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/05442

Abstract: An integrated circuit package (34, 34′, 34″) may be implemented by stacked first, second, and third integrated circuit dies (40, 50, 60). The first and second dies (40, 50) may be bonded to each other using corresponding inter-die connection structures (74-1, 84-1) at respective interfacial surfaces facing the other die. The second die (50) may also include a metal layer (84-2) for connecting to the third die (60) at its interfacial surface with the first die (40). The metal layer (84-2) may be connected to a corresponding inter-die connection structure (64) on the side of the third die (60) facing the second die (50) through a conductive through-substrate via (84-2) and an additional metal layer (102) in a redistribution layer (96) between the second and third dies (50, 60). The third die (60) may have a different lateral outline than the second die (50).