公开(公告)号：US07573136B2

公开(公告)日：2009-08-11

申请号：US11140422

申请日：2005-05-27

Applicant: Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A multidie semiconductor device assembly or package includes an interposer comprising a substrate with at least one receptacle therethrough. A plurality of semiconductor device components (e.g., semiconductor devices) may be assembled with the interposer. For example, at least one contact pad of a semiconductor device component adjacent to one surface of the interposer may be electrically connected to a corresponding contact pad of another semiconductor device component positioned adjacent to an opposite surface of the interposer. As another example, multiple semiconductor device components may be at least partially superimposed relative to one another and at least partially disposed within a receptacle of the interposer.

Abstract translation: 多元半导体器件组件或封装包括内插器，其包括具有穿过其中的至少一个插座的衬底。 多个半导体器件部件（例如，半导体器件）可以与插入器组装。 例如，与插入器的一个表面相邻的半导体器件部件的至少一个接触焊盘可以电连接到邻近插入器的相对表面定位的另一个半导体器件部件的对应接触焊盘。 作为另一示例，多个半导体器件部件可以至少部分地相对于彼此重叠并且至少部分地设置在插入器的插座内。

公开(公告)号：US07109572B2

公开(公告)日：2006-09-19

申请号：US10728413

申请日：2003-12-05

Applicant: Setho Sing Fee ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Lim Thiam Chye

IPC: H01L23/495 ,  H01R9/00

CPC classification number: H01L21/4842 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract translation: 公开了四平面无引线（QFN）栅格阵列半导体封装及其制造方法。 封装包括半导体管芯和引线框架，引线框架具有以栅格型阵列图案化的多个导电元件。 半导体管芯上的多个接合焊盘例如通过引线接合而耦合到多个导电元件。 半导体管芯和引线框架的至少一部分被封装在绝缘材料中，使导电元件沿着封装的底部主表面露出，以便随后与更高级别的封装电连接。 各个导电引线元件以及栅极阵列图案通过将多个接合焊盘引线接合到不同位置处的单个引线并随后在接合位置之间切断引线以形成来自每个引线的多个导电元件来形成。

公开(公告)号：US06906415B2

公开(公告)日：2005-06-14

申请号：US10184340

申请日：2002-06-27

Applicant: Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

Inventor： Tongbi Jiang ,  Setho Sing Fee ,  Tay Wuu Yean ,  Lim Thiam Chye

IPC: H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/40 ,  H01L23/34

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multidie semiconductor device (MDSCD) package includes a generally planar interposer comprising a substrate with a central receptacle, upper surface conductors, and outer connectors on the lower surface of the interposer. Conductive vias connect upper surface conductors with outer connectors. One or more semiconductor devices may be mounted in the receptacle and one or more other semiconductor devices mounted above and/or below the interposer and attached thereto. The package may be configured to have a footprint not significantly larger than the footprint of the largest device and/or a thickness not significantly greater than the combined thickness of included devices. Methods for assembling and encapsulating packages from multidie wafers and multi-interposer sheets or strips are disclosed. Methods for combining a plurality of packages into a single stacked package are disclosed. The methods may include use of somewhat laterally extending intermediate conductive elements, flip-chip style electrical connection, or both within the same package.

Abstract translation: 多芯片半导体器件（MDSCD）封装包括大体上平面的中介层，其包括具有中心插座的基板，上表面导体以及插入件下表面上的外部连接器。 导电通孔将上表面导体与外部连接器相连。 一个或多个半导体器件可以安装在插座中，以及安装在插入件上方和/或下方并附着于其上的一个或多个其它半导体器件。 封装可以被配置为具有不显着大于最大器件的占地面积和/或不显着大于所包括的器件的组合厚度的厚度。 公开了用于组装和封装来自多芯片晶片和多中介片片或条的封装的方法。 公开了将多个封装组合成单个堆叠封装的方法。 这些方法可以包括在相同封装内使用稍微侧向延伸的中间导电元件，倒装片式电连接或两者。

公开(公告)号：US06750534B2

公开(公告)日：2004-06-15

申请号：US10099284

申请日：2002-03-15

Applicant: Weddie Pacio Aquien ,  Loreto Y. Cantillep ,  Setho Sing Fee

Inventor： Weddie Pacio Aquien ,  Loreto Y. Cantillep ,  Setho Sing Fee

IPC: H01L23495

CPC classification number: H01L23/544 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/48 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2224/056 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K1/0269 ,  H05K3/303 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A new method is provided to identify semiconductor devices whereby the invention provides for a shallow depression on the backside of the heat sink of the ball grid array package. This shallow depression or hole can be used for visual and optical inspection of the device orientation.

Abstract translation: 提供了一种新的方法来识别半导体器件，由此本发明提供了球栅阵列封装的散热器背面上的浅凹陷。 该浅凹陷或孔可用于器件取向的视觉和光学检查。

公开(公告)号：US07528007B2

公开(公告)日：2009-05-05

申请号：US11411287

申请日：2006-04-25

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Steven W. Heppler ,  Leng Nam Yin ,  Keith Tan ,  Patrick Guay ,  Edmund Lua Koon Tian ,  Yap Kah Eng ,  Eric Tan Swee Seng

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Steven W. Heppler ,  Leng Nam Yin ,  Keith Tan ,  Patrick Guay ,  Edmund Lua Koon Tian ,  Yap Kah Eng ,  Eric Tan Swee Seng

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L21/568 ,  H01L21/4846 ,  H01L21/6835 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/50 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4911 ,  H01L2224/85001 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/19107 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method for assembling one or more semiconductor devices with an interposer includes positioning the one or more semiconductor devices within a receptacle that extends through the interposer, on a retention element that extends over at least a portion of the receptacle. Material may be introduced between at least a portion of an outer periphery of the one or more semiconductor devices and an inner periphery of the interposer to facilitate securing of the one or more semiconductor devices in place relative to the interposer. The retention element may be removed from the semiconductor devices. Once the one or more semiconductor devices are in place, they may be electrically connected to the interposer.

Abstract translation: 一种用于将一个或多个半导体器件与插入件组装的方法包括将一个或多个半导体器件定位在延伸穿过插入件的插座内，在保持元件上，该保持元件在容器的至少一部分上延伸。 可以在一个或多个半导体器件的外周的至少一部分与插入器的内周之间引入材料，以便于相对于插入件将一个或多个半导体器件固定在适当位置。 保留元件可以从半导体器件移除。 一旦一个或多个半导体器件就位，它们可以电连接到插入器。

公开(公告)号：US20080284000A1

公开(公告)日：2008-11-20

申请号：US11770451

申请日：2007-06-28

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Tongbi Jiang

IPC: H01L23/14 ,  H01L21/00

CPC classification number: H01L24/03 ,  H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Some embodiments include methods of assembling integrated circuit packages in which at least two different conductive layers are formed over a bond pad region of a semiconductor die, and in which a conductive projection associated with an interposer is bonded through a gold ball to an outermost of the at least two conductive layers. The conductive layers may comprise one or more of silver, gold, copper, chromium, nickel, palladium, platinum, tantalum, titanium, vanadium and tungsten. In some embodiments, the bond pad region may comprise aluminum, an inner of the conductive layers may comprise nickel, an outer of the conductive layers may comprise gold, the conductive projection associated with the interposer may comprise gold; and the thermosonic bonding may comprise gold-to-gold bonding of the interposer projection to a gold ball, and gold-to-gold bonding of the outer conductive layer to the gold ball. Some embodiments include integrated circuit packages.

Abstract translation: 一些实施例包括组装集成电路封装的方法，其中在半导体管芯的接合焊盘区域上形成至少两个不同的导电层，并且其中与插入件相关联的导电突起通过金球结合到 至少两个导电层。 导电层可以包括银，金，铜，铬，镍，钯，铂，钽，钛，钒和钨中的一种或多种。 在一些实施例中，接合焊盘区域可以包括铝，导电层的内部可以包括镍，导电层的外部可以包括金，与中介层相关联的导电突起可以包括金; 并且热超声键合可以包括插入物突起与金球的金 - 金结合，以及外导体层与金球的金 - 金结合。 一些实施例包括集成电路封装。

公开(公告)号：US07294911B2

公开(公告)日：2007-11-13

申请号：US10233159

申请日：2002-08-29

Applicant: Teck Kheng Lee ,  Tan Yong Kian ,  Setho Sing Fee

Inventor： Teck Kheng Lee ,  Tan Yong Kian ,  Setho Sing Fee

IPC: H01L23/495

CPC classification number: H01L21/4832 ,  H01L21/56 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49503 ,  H01L23/49551 ,  H01L23/49558 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A circuit package is formed using a leadframe. The leadframe is formed or etched to align a plurality of bond pad structures above a reference plane while supporting leadframe fingers are positioned below the reference plane. Jumper wires are wirebonded between terminals on the die and the bond pads to form a package subassembly. The subassembly is encapsulated and then background to remove the leadframe fingers and surrounding frame. The bond pads which remain embedded in the encapsulation material are exposed on the lower surface of the package for connection to further conductors.

Abstract translation: 使用引线框形成电路封装。 引导框架被形成或蚀刻以将多个接合焊盘结构对准在参考平面之上，同时支撑引线框架指状物位于参考平面的下方。 跳线在芯片上的端子和接合垫之间被引线键合以形成封装子组件。 子组件被封装，然后被背景去除引线框架指状物和周围框架。 保留在封装材料中的接合焊盘暴露在封装的下表面上，以连接到另外的导体。

公开(公告)号：US07279780B2

公开(公告)日：2007-10-09

申请号：US11215620

申请日：2005-08-30

Applicant: Setho Sing Fee ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Lim Thiam Chye

IPC: H01L23/495 ,  H01L21/00 ,  H01R9/00

CPC classification number: H01L21/4842 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same are provided. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the leads between the bonding locations to form multiple conductive elements from each individual lead.

Abstract translation: 提供四边形无引线（QFN）栅格阵列半导体封装及其制造方法。 封装包括半导体管芯和引线框架，引线框架具有以栅格型阵列图案化的多个导电元件。 半导体管芯上的多个接合焊盘例如通过引线接合而耦合到多个导电元件。 半导体管芯和引线框架的至少一部分被封装在绝缘材料中，使导电元件沿着封装的底部主表面露出，以便随后与更高级别的封装电连接。 各个导电引线元件以及栅极阵列图案通过将多个接合焊盘引线接合到不同位置处的单个引线并随后在接合位置之间切断引线以形成来自每个引线的多个导电元件来形成。

公开(公告)号：US06967125B2

公开(公告)日：2005-11-22

申请号：US09933297

申请日：2001-08-20

Applicant: Setho Sing Fee ,  Lim Thiam Chye

Inventor： Setho Sing Fee ,  Lim Thiam Chye

IPC: H01L21/48 ,  H01L23/31 ,  H01L23/495 ,  H01L21/44 ,  H01L21/302 ,  H01L21/469 ,  H01L21/50

CPC classification number: H01L21/4842 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A quad flat no-lead (QFN) grid array semiconductor package and method for making the same is disclosed. The package includes a semiconductor die and a lead frame having a plurality of conductive elements patterned in a grid-type array. A plurality of bond pads on the semiconductor die is coupled to the plurality of conductive elements, such as by wire bonding. The semiconductor die and at least a portion of the lead frame are encapsulated in an insulative material, leaving the conductive elements exposed along a bottom major surface of the package for subsequent electrical connection with higher-level packaging. Individual conductive lead elements, as well as the grid array pattern, are formed by wire bonding multiple bond pads to a single lead at different locations and subsequently severing the lead between the bonding locations to form multiple conductive elements from each individual lead.

Abstract translation: 公开了四平面无引线（QFN）栅格阵列半导体封装及其制造方法。 封装包括半导体管芯和引线框架，引线框架具有以栅格型阵列图案化的多个导电元件。 半导体管芯上的多个接合焊盘例如通过引线接合而耦合到多个导电元件。 半导体管芯和引线框架的至少一部分被封装在绝缘材料中，使导电元件沿着封装的底部主表面露出，以便随后与更高级别的封装电连接。 各个导电引线元件以及栅极阵列图案通过将多个接合焊盘引线接合到不同位置处的单个引线并随后在接合位置之间切断引线以形成来自每个引线的多个导电元件而形成。

公开(公告)号：US06943450B2

公开(公告)日：2005-09-13

申请号：US10929613

申请日：2004-08-30

Applicant: Setho Sing Fee ,  Lim Thiam Chye ,  Eric Tan Swee Seng

Inventor： Setho Sing Fee ,  Lim Thiam Chye ,  Eric Tan Swee Seng

IPC: H01L21/56 ,  H01L21/68 ,  H01L23/31 ,  H01L23/495 ,  H01L23/48

CPC classification number: H01L21/568 ,  H01L21/56 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49558 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/4943 ,  H01L2224/85001 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Microelectronic devices in accordance with aspects of the invention may include a die, a plurality of lead fingers and an encapsulant which may bond the lead fingers and the die. In one method of the invention, a lead frame and a die are releasably attached to a support, an encapsulant is applied, and the support can be removed to expose back contacts of the lead fingers and a back surface of the die. One microelectronic device assembly of the invention includes a die having an exposed back die surface; a plurality of electrical leads, each of which includes front and back electrical contacts; bonding wires electrically coupling the die to the electrical leads; and an encapsulant bonded to the die and the electrical leads. The rear electrical contacts of the electrical leads may be exposed adjacent a back surface of the encapsulant in a staggered array.