公开(公告)号：US20160343418A1

公开(公告)日：2016-11-24

申请号：US15228644

申请日：2016-08-04

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott Best ,  Lei Luo ,  Ian Shaeffer

IPC: G11C7/22 ,  G11C29/50 ,  G11C29/56

CPC classification number: G11C7/222 ,  G11C7/227 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US20160293236A1

公开(公告)日：2016-10-06

申请号：US15081745

申请日：2016-03-25

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Kyung Suk Oh

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/18 ,  G11C11/4063 ,  G11C11/4097 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028

Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.

公开(公告)号：US20160019171A1

公开(公告)日：2016-01-21

申请号：US14866911

申请日：2015-09-26

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G06F13/362

CPC classification number: G06F13/1694 ,  G06F13/287 ,  G06F13/3625 ,  G06F13/4221 ,  G06F13/4234

Abstract: A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is transferred over the bus at one rate when accessing one type of memory device and at a different rate when accessing another type of memory device. In addition, the memory controller may provide control information (e.g., command and address information) to the different types of memory devices at different rates and, in some cases, time multiplex the control information on a shared bus.

Abstract translation: 存储器控制器通过使用时分复用总线来访问以不同本机速率运行的不同类型的存储器件。 当访问一种类型的存储设备时，以一种速率通过总线传送数据，并且在访问另一种类型的存储设备时以不同的速率传输数据。 此外，存储器控制器可以以不同的速率向不同类型的存储器件提供控制信息（例如，命令和地址信息），并且在一些情况下，将共享总线上的控制信息进行时间复用。

公开(公告)号：US20160011933A1

公开(公告)日：2016-01-14

申请号：US14864500

申请日：2015-09-24

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Craig E. Hampel

IPC: G06F11/10 ,  H03M13/09

CPC classification number: G06F11/1004 ,  G06F11/0703 ,  G06F11/073 ,  G06F11/1679 ,  H03M13/09

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation

Abstract translation: 提供了用于检测和校正存储器系统中的地址错误的系统和方法。 在存储器系统中，存储器件基于通过地址总线发送的地址生成错误检测码，并将错误检测码发送到存储器控制器。 存储器控制器响应于错误检测码向存储器件发送错误指示。 错误指示使存储器件移除接收的地址并防止存储器操作

公开(公告)号：US20150332746A1

公开(公告)日：2015-11-19

申请号：US14813028

申请日：2015-07-29

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Lawrence Lai ,  Fan Ho ,  David A. Secker ,  Wayne S. Richardson ,  Akash Bansal ,  Brian S. Leibowitz ,  Kyung Suk Oh

IPC: G11C8/12 ,  G11C8/18 ,  G11C5/02

CPC classification number: G11C8/12 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C7/1012 ,  G11C7/1045 ,  G11C8/18 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Abstract translation: 描述了包括可编程命令和地址（CA）接口和/或可编程数据接口的存储器件。 在操作模式下，两个或多个CA接口可能处于活动状态。 在另一操作模式中，至少一个但不是全部的CA接口可能是活动的。 在操作模式下，所有数据接口都可能处于活动状态。 在另一种操作模式中，至少一个但不是全部的数据接口可能是活动的。 存储器装置可以包括用于选择：操作模式的电路; 操作模式中的子模式; 一个或多个CA接口作为活动CA接口; 来自多个活动CA接口的主CA接口; 和/或一个或多个数据接口作为活动数据接口。 电路可以基于一个或多个寄存器中的一个或多个位和/或在一个或多个引脚上接收到的一个或多个信号来执行这些选择。

公开(公告)号：US20150243343A1

公开(公告)日：2015-08-27

申请号：US14702582

申请日：2015-05-01

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Alok Gupta ,  Ian Shaeffer ,  Steven C. Woo

IPC: G11C11/4076 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G06F1/08 ,  G06F3/0629 ,  G06F3/0634 ,  G06F5/06 ,  G06F12/0646 ,  G06F13/1689 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C11/409 ,  G11C11/4096 ,  G11C2207/2254

Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.

公开(公告)号：US09117035B2

公开(公告)日：2015-08-25

申请号：US14015648

申请日：2013-08-30

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G06F12/00 ,  G06F13/40 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C7/10 ,  H01L25/065 ,  H01L25/10 ,  G11C7/22 ,  H01L25/18

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20150162092A1

公开(公告)日：2015-06-11

申请号：US14625505

申请日：2015-02-18

Applicant: Rambus Inc.

Inventor： Brent Haukness ,  Ian Shaeffer

IPC: G11C16/32 ,  G06F12/02 ,  G11C16/10

CPC classification number: G11C16/32 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C16/04 ,  G11C16/107 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/4402

Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.

Abstract translation: 本公开提供了一种准确地确定与诸如设备，块或页面之类的闪速存储器细分有关的预期交易时间的方法。 通过执行测试事务来对每个这样的单元的每个位进行编程，可以预先确定每个单元的最大预期编程时间并用于调度目的。 例如，在简单的实现中，可以识别相对精确的经验测量的时间限制并用于有效地管理和调度闪速存储器事务，而不等待最终解决写入非响应页面的尝试。 本公开还提供经验测量的最大闪存交易时间的其他用途，包括经由多个存储器模式和优先存储器; 例如，如果需要高性能模式，则可以容忍闪速存储器交易时间的低变化，并且可以相对快速地标记不满足这些原理的单元。

公开(公告)号：US20150023118A1

公开(公告)日：2015-01-22

申请号：US14509572

申请日：2014-10-08

Applicant: RAMBUS INC.

Inventor： Ian Shaeffer ,  Frederick Ware ,  Craig E. Hampel

IPC: G06F3/06 ,  G11C7/22

CPC classification number: G06F3/0634 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/1694 ,  G06F2212/262 ,  G11C7/22

Abstract: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.

Abstract translation: 在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。 例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。 在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考 数据信号。 也可以针对不同的操作模式调用不同的数据掩码相关方案。 例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。 然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

公开(公告)号：US20140347950A1

公开(公告)日：2014-11-27

申请号：US14194923

申请日：2014-03-03

Applicant: Rambus Inc.

Inventor： Ian Shaeffer

IPC: G11C8/16 ,  G11C8/06

CPC classification number: G11C8/16 ,  G06F12/00 ,  G06F13/4018 ,  G06F13/4243 ,  G11C8/06

Abstract: Described are memory modules that support dynamic point-to-point extensibility using fixed-width memory die. The memory modules include data-width translators that allow the modules to vary the effective width of their external memory interfaces without varying the width of the internal memory interfaces extending between the translators and associated fixed-width dies. The data-width translators use a data-mask signal to selectively prevent memory accesses to subsets of physical addresses. This data masking divides the physical address locations into two or more temporal subsets of the physical address locations, effectively increasing the number of uniquely addressable locations in a given module. Reading temporal addresses in write order can introduce undesirable read latency. Some embodiments reorder read data to reduce this latency.

Abstract translation: 描述的是使用固定宽度内存模块支持动态点对点可扩展性的内存模块。 存储器模块包括数据宽度转换器，其允许模块改变其外部存储器接口的有效宽度，而不改变在转换器和相关联的固定宽度管芯之间延伸的内部存储器接口的宽度。 数据宽度转换器使用数据掩码信号来选择性地阻止对物理地址子集的存储器访问。 该数据屏蔽将物理地址位置划分为物理地址位置的两个或更多个时间子集，从而有效地增加给定模块中唯一可寻址位置的数量。 以写入顺序读取时间地址可能会引入不期望的读取延迟。 一些实施例重新排序读取数据以减少该等待时间。