公开(公告)号：US20180025907A1

公开(公告)日：2018-01-25

申请号：US15654185

申请日：2017-07-19

Applicant: Applied Materials, Inc.

Inventor： Lakmal C. Kalutarage ,  Mark Saly ,  David Thompson ,  Abhijit Basu Mallick ,  Tejasvi Ashok ,  Pramit Manna

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/02274 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/76224

Abstract: Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill.

公开(公告)号：US20170372919A1

公开(公告)日：2017-12-28

申请号：US15630479

申请日：2017-06-22

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Abhijit Basu Mallick ,  Karthik Janakiraman

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L21/32115 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/32053 ,  H01L21/32055

Abstract: Methods for seam-less gapfill comprising forming a flowable film by PECVD and curing the flowable film to solidify the film. The flowable film can be formed using a higher order silane and plasma. A UV cure, or other cure, can be used to solidify the flowable film.

公开(公告)号：US09840777B2

公开(公告)日：2017-12-12

申请号：US14468665

申请日：2014-08-26

Applicant: Applied Materials, Inc.

Inventor： Jianhua Zhou ,  Juan Carlos Rocha-Alvarez ,  Yihong Chen ,  Abhijit Basu Mallick ,  Oscar Lopez ,  Ningli Liu

IPC: C23C16/455 ,  C23C16/458 ,  C23C16/509 ,  H01J37/32

CPC classification number: C23C16/45565 ,  C23C16/45574 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/5096 ,  H01J37/32357 ,  H01J37/32422 ,  H01J37/32449

Abstract: Embodiments disclosed herein generally include an apparatus for radical-based deposition of dielectric films. The apparatus includes a processing chamber, a radical source coupled to the processing chamber, a substrate support disposed in the processing chamber, and a dual-channel showerhead disposed between the radical source and the substrate support. The dual-channel showerhead includes a plurality of tubes and an internal volume surrounding the plurality of tubes. The plurality of tubes and the internal volume are surrounded by one or more annular channels embedded in the dual-channel showerhead. The dual-channel showerhead further includes a first inlet connected to the one or more channels and a second inlet connected to the internal volume. The processing chamber may be a PECVD chamber, and the apparatus is capable of performing a cyclic process (alternating radical based CVD and PECVD).

公开(公告)号：US09624577B2

公开(公告)日：2017-04-18

申请号：US14697385

申请日：2015-04-27

Applicant: Applied Materials, Inc.

Inventor： Pramit Manna ,  Abhijit Basu Mallick ,  Mukund Srinivasan ,  Rui Cheng

IPC: C23F1/02 ,  C23C16/26 ,  C23C16/04 ,  C23C16/06 ,  H01J37/32 ,  C23C16/30

CPC classification number: C23C16/26 ,  C23C16/042 ,  C23C16/06 ,  C23C16/30 ,  H01J37/32091

Abstract: Embodiments of the present disclosure relate to a metal-doped amorphous carbon hardmask for etching the underlying layer, layer stack, or structure. In one embodiment, a method of processing a substrate in a processing chamber includes exposing a substrate to a gas mixture comprising a carbon-containing precursor and a metal-containing precursor, reacting the carbon-containing precursor and the metal-containing precursor in the processing chamber to form a metal-doped carbon layer over a surface of the substrate, forming in the metal-doped carbon layer a defined pattern of through openings, and transferring the defined pattern to an underlying layer beneath the metal-doped carbon layer using the metal-doped carbon layer as a mask. An etch hardmask using the inventive metal-doped amorphous carbon film provides reduced compressive stress, high hardness, and therefore higher etch selectivity.

公开(公告)号：US09368448B2

公开(公告)日：2016-06-14

申请号：US14268727

申请日：2014-05-02

Applicant: Applied Materials, Inc.

Inventor： Yihong Chen ,  Abhijit Basu Mallick ,  Mehul B. Naik ,  Srinivas D. Nemani

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

Abstract translation: 提供一种用于形成用于半导体器件的互连结构的方法。 该方法首先在衬底上形成低k体积电介质层，然后在低k体电介质层中形成沟槽。 衬底层形成在与沟槽共形沉积的低k体积电介质层上。 在填充沟槽的衬垫层上形成铜层。 去除部分铜层和衬层以形成低k体电介质层，衬里层和铜层的上表面。 在低k体电介质层，衬垫层和铜层的上表面上形成含金属的电介质层。

公开(公告)号：US08986557B2

公开(公告)日：2015-03-24

申请号：US14177893

申请日：2014-02-11

Applicant: Applied Materials, Inc.

Inventor： Brian Saxton Underwood ,  Abhijit Basu Mallick ,  Nitin Ingle ,  Roman Gouk ,  Steven Verhaverbeke

IPC: B44C1/22 ,  G11B5/85 ,  G11B5/855

CPC classification number: G11B5/85 ,  G11B5/855

Abstract: Method and apparatus for forming a patterned magnetic substrate are provided. A patterned resist is formed on a magnetically active surface of a substrate. An oxide layer is formed over the patterned resist by a flowable CVD process. The oxide layer is etched to expose portions of the patterned resist. The patterned resist is then etched, using the etched oxide layer as a mask, to expose portions of the magnetically active surface. A magnetic property of the exposed portions of the magnetically active surface is then modified by directing energy through the etched resist layer and the etched oxide layer, which are subsequently removed from the substrate.

Abstract translation: 提供了用于形成图案化磁性基底的方法和装置。 在基板的磁性活性表面上形成图案化的抗蚀剂。 通过可流动的CVD工艺在图案化的抗蚀剂上形成氧化物层。 蚀刻氧化物层以暴露图案化抗蚀剂的部分。 然后使用蚀刻的氧化物层作为掩模蚀刻图案化的抗蚀剂，以暴露磁性活性表面的部分。 然后通过将能量引导通过经蚀刻的抗蚀剂层和经蚀刻的氧化物层（随后从衬底去除）来改变磁性活性表面的暴露部分的磁性。

公开(公告)号：US08889566B2

公开(公告)日：2014-11-18

申请号：US13668657

申请日：2012-11-05

Applicant: Applied Materials, Inc.

Inventor： Amit Chatterjee ,  Abhijit Basu Mallick ,  Nitin K. Ingle ,  Brian Underwood ,  Kiran V. Thadani ,  Xiaolin Chen ,  Abhishek Dube ,  Jingmei Liang

IPC: C23C16/32 ,  C23C16/34 ,  C23C16/50 ,  H01L21/02 ,  H01L21/31 ,  H01L21/318

CPC classification number: H01L21/02274 ,  C23C16/401 ,  C23C16/505 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02219

Abstract: A method of forming a dielectric layer is described. The method deposits a silicon-containing film by chemical vapor deposition using a local plasma. The silicon-containing film is flowable during deposition at low substrate temperature. A silicon precursor (e.g. a silylamine, higher order silane or halogenated silane) is delivered to the substrate processing region and excited in a local plasma. A second plasma vapor or gas is combined with the silicon precursor in the substrate processing region and may include ammonia, nitrogen (N2), argon, hydrogen (H2) and/or oxygen (O2). The equipment configurations disclosed herein in combination with these vapor/gas combinations have been found to result in flowable deposition at substrate temperatures below or about 200° C. when a local plasma is excited using relatively low power.

Abstract translation: 描述形成电介质层的方法。 该方法通过使用局部等离子体的化学气相沉积法沉积含硅膜。 含硅膜在低基板温度下沉积时是可流动的。 将硅前体（例如甲硅烷基胺，高级硅烷或卤代硅烷）输送到衬底处理区域并在局部等离子体中激发。 第二等离子体蒸气或气体与硅衬底加工区域中的硅前体结合，并且可包括氨，氮（N 2），氩，氢（H 2）和/或氧（O 2）。 已经发现本文公开的与这些蒸汽/气体组合组合的设备结构在基板温度低于或约200℃时导致可流动的沉积，当使用较低功率激发局部等离子体时。

公开(公告)号：US20140273430A1

公开(公告)日：2014-09-18

申请号：US14180098

申请日：2014-02-13

Applicant: Applied Materials, Inc.

Inventor： Mehul B. NAIK ,  Abhijit Basu Mallick ,  Kiran V. Thadani ,  Zhenjiang Cui

IPC: H01L21/768 ,  H01L21/56

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

Abstract translation: 本发明的实施例一般涉及用于形成金属结构和钝化层的方法。 在一个实施例中，在衬底上形成金属柱。 金属柱掺杂有锰，铝，锆或铪。 介电材料沉积在金属柱之上和之间，然后固化以在金属柱的垂直表面上形成钝化层。

公开(公告)号：US20250054748A1

公开(公告)日：2025-02-13

申请号：US18232133

申请日：2023-08-09

Applicant: Applied Materials, Inc.

Inventor： Guangyan Zhong ,  Jongbeom Seo ,  Eswaranand Venkatasubramanian ,  Abhijit Basu Mallick

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/50 ,  H01J37/32 ,  H01L21/285

Abstract: Exemplary methods of semiconductor processing may include providing a treatment precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The methods may include contacting a surface of the substrate with the treatment precursor. The methods may include providing deposition precursors to the processing region. The deposition precursors may include a metal-containing precursor. The methods may include forming plasma effluents of the deposition precursors. The methods may include contacting the substrate with the plasma effluents of the deposition precursors. The contacting may deposit a metal-containing hardmask on the substrate.

公开(公告)号：US20240194757A1

公开(公告)日：2024-06-13

申请号：US18383182

申请日：2023-10-24

Applicant: Applied Materials, Inc.

Inventor： Sai Hooi Yeong ,  Liu Jiang ,  Susmit Singha Roy ,  Abhijit Basu Mallick ,  El Mehdi Bazizi ,  Benjamin Colombeau

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.