公开(公告)号：US20180151690A1

公开(公告)日：2018-05-31

申请号：US15875055

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L29/66795 ,  H01L29/785

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US09935104B1

公开(公告)日：2018-04-03

申请号：US15589292

申请日：2017-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Wei Zhao ,  Hong Yu ,  Xusheng Wu ,  Hui Zang ,  Zhenyu Hu

IPC: H01L21/84 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/762 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649

Abstract: Disclosed is a semiconductor structure, including at least one fin-type field effect transistor and at least one single-diffusion break (SDB) type isolation region, and a method of forming the semiconductor structure. In the method, an isolation bump is formed above an isolation region within a semiconductor fin and sidewall spacers are formed on the bump. During an etch process to reduce the height of the bump and to remove isolation material from the sidewalls of the fin, the sidewall spacers prevent lateral etching of the bump. During an etch process to form source/drain recesses in the fin, the sidewalls spacers protect the semiconductor material adjacent to the isolation region. Consequently, the sides and bottom of each recess include semiconductor surfaces and the angle of the top surfaces of the epitaxial source/drain regions formed therein is minimized, thereby minimizing the risk of unlanded source/drain contacts.

公开(公告)号：US09653583B1

公开(公告)日：2017-05-16

申请号：US15226165

申请日：2016-08-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Zhao ,  Haiting Wang ,  Hongliang Shen ,  Zhenyu Hu ,  Min-Hwa Chi

IPC: H01L21/8238 ,  H01L21/66 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3105

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823857 ,  H01L21/823878 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes, among other things, forming a first gate structure above a fin, forming epi semiconductor material on the fin, performing at least one first etching process through a patterned sacrificial layer of material to remove at least a gate cap layer and sacrificial gate materials of the first gate structure so as to define a first isolation cavity that exposes the fin while leaving the second gate structure intact, performing at least one second etching process through the first isolation cavity to remove at least a portion of a vertical height of the fin and thereby form a first isolation trench, removing the patterned sacrificial layer of material, and forming a layer of insulating material above the epi semiconductor material and in the first isolation trench and in the first isolation cavity.

公开(公告)号：US20160190130A1

公开(公告)日：2016-06-30

申请号：US14676165

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhenyu Hu ,  Jin Ping Liu

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/306 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/28 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/3105

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7851

Abstract: A method includes forming a fin in a semiconductor substrate. A plurality of sacrificial gate structures are formed above the fin. A selected one of the sacrificial gate structures is removed to define a first opening that exposes a portion of the fin. An etch process is performed through the first opening on the exposed portion of the fin to define a first recess in the fin. The first recess is filled with a dielectric material to define a diffusion break in the fin. A device includes a fin defined in a substrate, a plurality of gates formed above the fin, a plurality of recesses filled with epitaxial material defined in the fin, and a diffusion break defined at least partially in the fin between two of the recesses filled with epitaxial material and extending above the fin.

Abstract translation: 一种方法包括在半导体衬底中形成翅片。 在翅片上形成多个牺牲栅极结构。 去除所选择的牺牲栅极结构之一以限定暴露鳍片的一部分的第一开口。 通过翅片的暴露部分上的第一开口进行蚀刻处理，以限定翅片中的第一凹部。 第一凹部填充有电介质材料以限定散热片中的扩散断裂。 一种装置包括限定在衬底中的翅片，形成在鳍片上方的多个栅极，填充有限定在翅片中的外延材料的多个凹槽以及至少部分地限定在翅片中的两个凹陷之间的扩散断裂， 外延材料并在翅片上方延伸。

公开(公告)号：US20200273953A1

公开(公告)日：2020-08-27

申请号：US16287365

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Chu ,  Wei Ma ,  Jae Gon Lee ,  Hong Yu ,  Zhenyu Hu ,  Srikanth Balaji Samavedam

IPC: H01L29/10 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092

Abstract: One illustrative integrated circuit product disclosed herein includes a short-channel transistor device and a long-channel transistor device formed above a semiconductor substrate, wherein a first gate structure for the short-channel transistor device includes a short-channel WFM layer with a first upper surface that is positioned at a first distance above an upper surface of the semiconductor substrate, and wherein a second gate structure for the long-channel transistor device includes a long-channel WFM layer with a second upper surface that is positioned at a second distance above the upper surface of the semiconductor substrate, wherein the first distance is greater than the second distance.

公开(公告)号：US20200243645A1

公开(公告)日：2020-07-30

申请号：US16262052

申请日：2019-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hong ,  George R. Mulfinger ,  Hui Zang ,  Liu Jiang ,  Zhenyu Hu

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78

Abstract: One illustrative method disclosed herein may include forming a first straight sidewall spacer adjacent a gate structure of a transistor, forming a recessed layer of sacrificial material adjacent the first straight sidewall spacer and forming a second straight sidewall spacer on a portion of the outer surface of the first straight sidewall spacer and above the recessed layer of sacrificial material. The method may also include removing the recessed layer of sacrificial material so as to expose a first vertical portion of the outer surface of the first straight sidewall spacer and forming an epi material on and above the substrate, wherein an edge of the epi material engages the first straight sidewall spacer.

公开(公告)号：US10431665B2

公开(公告)日：2019-10-01

申请号：US15875055

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tao Han ,  Zhenyu Hu ,  Jinping Liu ,  Hsien-Ching Lo ,  Jianwei Peng

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Structures for spacers in a device structure for a field-effect transistor and methods for forming spacers in a device structure for a field-effect transistor. A first spacer is located adjacent to a vertical sidewall of a gate electrode, a second spacer located between the first spacer and the vertical sidewall of the gate electrode, and a third spacer located between the second spacer and the vertical sidewall of the gate electrode. The first spacer has a higher dielectric constant than the second spacer. The first spacer has a higher dielectric constant than the third spacer. The third spacer has a lower dielectric constant than the second spacer.

公开(公告)号：US10355104B2

公开(公告)日：2019-07-16

申请号：US15795833

申请日：2017-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Sang Woo Lim ,  Kyung-Bum Koo ,  Alina Vinslava ,  Pei Zhao ,  Zhenyu Hu ,  Hsien-Ching Lo ,  Joseph F. Shepard, Jr. ,  Shesh Mani Pandey

IPC: H01L21/02 ,  H01L21/84 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08

Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region beneath a top surface of a semiconductor fin. The semiconductor fin is etched with an anisotropic etching process to form a cavity having a sidewall with a planar section extending vertically toward the top surface of the semiconductor fin and adjacent to the channel region in the semiconductor fin. The semiconductor fin is then etched with an isotropic etching process that widens the cavity at the top surface while preserving verticality of the planar section.

公开(公告)号：US10192746B1

公开(公告)日：2019-01-29

申请号：US15665183

申请日：2017-07-31

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ashish Kumar Jha ,  Hui Zhan ,  Hong Yu ,  Zhenyu Hu ,  Haiting Wang ,  Edward Reis ,  Charles Vanleuvan

IPC: H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/475

Abstract: A shallow trench isolation (STI) structure is formed from a conventional STI trench structure formed of first dielectric material extending into the substrate. The conventional STI structure undergoes further processing, including removing a first portion of the dielectric material and adjacent portions of the semiconductor substrate to create a first recess, and then removing another portion of the dielectric material to create a second recess in just the dielectric material. A nitride layer is formed above remaining dielectric material and on the sidewalls of the substrate. A second dielectric material is formed on the spacer layer and fills the remainder of first and second recesses. The nitride layer provides an “inner spacer” between the first insulating material and the second insulating material and also separates the substrate from the second insulating material. An isotropic Fin reveal process is performed and the STI structure assists in equalizing fin heights and increasing active S/D region area/volume.

公开(公告)号：US20150200111A1

公开(公告)日：2015-07-16

申请号：US14153120

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sruthi Muralidharan ,  Zhenyu Hu ,  Qi Zhang ,  Ja-Hyung Han ,  Dinesh Koli ,  Zhuangfei Chen

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/32115 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity.

Abstract translation: 本发明的实施例提供了用于制造finFET的改进方法。 在finFET制造期间，诸如非晶硅的膜沉积在半导体衬底上，该半导体衬底具有鳍片和不具有鳍片的区域。 填充层沉积在膜上并且被平坦化以形成齐平表面。 使用凹陷或蚀刻工艺来形成平坦表面，其中填充层的所有部分被去除。 可以使用诸如气体簇离子束工艺的精加工工艺来进一步平滑衬底表面。 这导致在结构（例如半导体晶片）上具有非常均匀的厚度的膜，导致晶片内（WiW）的均匀性提高和芯片内（WiC）均匀性提高。