摘要:
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要:
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要:
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要:
A resin composition having superior molding character, bonding character, moisture resistance, and heat resistance, for encapsulating of a semiconductor which contains:(a) An ether imide group compound represented by the general formula (I) ##STR1## wherein, each of R.sup.1 -R.sup.4, R.sup.8 and R.sup.8 is hydrogen, lower alkyl group, lower alkoxy group, lower fluoroalkyl group, chlorine or bromine, and R.sup.1 -R.sup.4, R.sup.7 and R.sup.8 may be same or different each other, and each of R.sup.5 and R.sup.6 is hydrogen, methyl group, ethyl group, trifluoromethyl group or trichloromethyl group, and R.sup.5 and R.sup.6 may be same or different each other, and D is a hydrocarbon group of a dicarboxylic acid having an ethylene type unsaturated double bond of an extract of the compound obtained by extraction with water in an amount 10 times by weight of the compound at 120.degree. C. for more than 100 hours has electric conductivity of at most 300 s/cm ph of 1.5-7; and(b) an epoxy resin as well as a semiconductor apparatus encapsulated with the resin.
摘要:
A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device. The electrically insulating layer is formed with a thickness so as to provide α-ray shielding of the semiconductor device.
摘要:
A semiconductor apparatus comprising a semiconductor device, an electrically insulating layer formed on the semiconductor device, and an external connection terminal formed on the electrically insulating layer and electrically connected to an electrode of the semiconductor device, wherein a power/ground line and a signal line in a region of from an edge of the electrically insulating layer to a uniform-thickness flat portion of the electrically insulating layer are different in kind of wiring pattern from each other.
摘要:
A semiconductor apparatus in which flip chip bonding is enabled without any underfill, and which comprises a semiconductor device, an electrically insulating layer formed on the semiconductor device by mask-printing an electrically insulating material containing particles, and an external connection terminal formed on the electrically insulating layer and electrically connected with an electrode of the semiconductor device.
摘要:
A semiconductor device is provided which enables a flip chip connection without use of underfill. The semiconductor device includes a semiconductor element having circuit electrodes and a circuit surface coated with a protecting film. A stress relaxation layer is provided by coating a cured thermoplastic resin onto the protecting film of the circuit surface in a manner which leaves the circuit electrodes exposed and curing it and having an inclination in the edge portion thereof. A wiring layer with wirings is connected to each of the circuit electrodes and disposed so as to make an electrical connection from the circuit electrodes, via the edge portion of the stress relaxation layer, and to a desired portion on the surface of the stress relaxation layer. A protecting film is provided thereon, and an external connection terminal is also provided.
摘要:
A semiconductor apparatus includes a semiconductor device having circuit electrodes aligned centrally of the semiconductor apparatus. A first electrically insulating layer is formed on said semiconductor device with said circuit electrodes being exposed from said first insulating layer. A second electrically insulating layer is formed on said first insulating layer, and external connection terminals are formed on said second insulating layer. A wiring is formed on said second insulating layer to electrically connect said external connect terminals to said circuit electrodes of said semiconductor device, and a third electrically insulating layer is formed on said second insulating layer and on said wiring. Particles are provided in the second insulating layer to control a shape of said second insulating layer.
摘要:
There is provided a conductive sintered layer forming composition and a conductive sintered layer forming method that can lower heating temperature and shorten heating time for a process of accelerating sintering or bonding by sintering of metal nano-particles coated with an organic substance. The conductive sintered layer forming composition may be obtained by utilizing a phenomenon that particles may be sintered at low temperature by mixing silver oxide with metal particles coated with the organic substance and having a grain size of 1 nm to 5 μm as compared to sintering each simple substance. The conductive sintered layer forming composition of the invention is characterized in that it contains the metal particles whose surface is coated with the organic substance and whose grain size is 1 nm to 5 μm and the silver oxide particles.