公开(公告)号：US07084479B2

公开(公告)日：2006-08-01

申请号：US10731377

申请日：2003-12-08

申请人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

发明人： Shyng-Tsong Chen ,  Stefanie Ruth Chiras ,  Matthew Earl Colburn ,  Timothy Joseph Dalton ,  Jeffrey Curtis Hedrick ,  Elbert Emin Huang ,  Kaushik Arun Kumar ,  Michael Wayne Lane ,  Kelly Malone ,  Chandrasekhar Narayan ,  Satyanarayana Venkata Nitta ,  Sampath Purushothaman ,  Robert Rosenburg ,  Christy Sensenich Tyberg ,  Roy RongQing Yu

IPC分类号： H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76829 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a multilevel microelectronic integrated circuit, air comprises permanent line level dielectric and ultra low-K materials are via level dielectric. The air is supplied to line level subsequent to removal of sacrificial material by clean thermal decomposition and assisted diffusion of byproducts through porosities in the IC structure. Optionally, air is also included within porosities in the via level dielectric. By incorporating air to the extent produced in the invention, intralevel and interlevel dielectric values are minimized.

公开(公告)号：US06975032B2

公开(公告)日：2005-12-13

申请号：US10319967

申请日：2002-12-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

公开(公告)号：US06927472B2

公开(公告)日：2005-08-09

申请号：US09992344

申请日：2001-11-14

申请人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

发明人： David K. Anderson ,  Tien-Jen Cheng ,  Timothy J. Dalton ,  Christopher V. Jahnes ,  Andrew Lu ,  Chandrasekhar Narayan ,  Kevin S. Petrarca ,  Richard P. Volant ,  George F. Walker

IPC分类号： H01L23/525 ,  H01L21/336

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

公开(公告)号：US20050104217A1

公开(公告)日：2005-05-19

申请号：US10707075

申请日：2003-11-19

申请人： Chandrasekhar Narayan ,  Kevin Petrarca

发明人： Chandrasekhar Narayan ,  Kevin Petrarca

IPC分类号： H01L23/48 ,  H01L23/485

CPC分类号： H01L24/10 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.

摘要翻译： 集成电路（IC）芯片，具有多个芯片位置的IC芯片的半导体晶片以及在晶片上制造IC芯片的方法。 IC芯片具有电镀芯片互连焊盘。 每个电镀垫包括电镀到可镀金属层的贵金属镀层。 可镀金属层可以是铜，贵金属镀层可以是金，铂，钯，铑，钌，锇，铱或铟。

公开(公告)号：US20050023664A1

公开(公告)日：2005-02-03

申请号：US10930304

申请日：2004-08-31

申请人： Michael Chudzik ,  Robert Dennard ,  Rama Divakaruni ,  Bruce Kenneth Furman ,  Rajarao Jammy ,  Chandrasekhar Narayan ,  Sampath Purushothaman ,  Joseph Shepard ,  Anna Wanda Topol

发明人： Michael Chudzik ,  Robert Dennard ,  Rama Divakaruni ,  Bruce Kenneth Furman ,  Rajarao Jammy ,  Chandrasekhar Narayan ,  Sampath Purushothaman ,  Joseph Shepard ,  Anna Wanda Topol

IPC分类号： H01L23/12 ,  H01L23/50 ,  H01L25/04 ,  H01L25/18 ,  H01L29/40 ,  H05K1/16 ,  H05K3/46 ,  H01L21/44 ,  H01L23/02 ,  H01L23/52

CPC分类号： H05K1/162 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2924/01019 ,  H01L2924/01055 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/30105 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/09809

摘要： A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.

摘要翻译： 提供了一种用于半导体部件的载体，其具有集成在其基板中的无源部件。 无源组件包括去耦组件，例如电容器和电阻器。 一组连接被集成以提供与受支持的部件的紧密的电气接近。

公开(公告)号：US06486526B1

公开(公告)日：2002-11-26

申请号：US09223826

申请日：1999-01-04

申请人： Chandrasekhar Narayan ,  Edward W. Kiewra ,  Carl J. Radens ,  Axel C. Brintzinger

发明人： Chandrasekhar Narayan ,  Edward W. Kiewra ,  Carl J. Radens ,  Axel C. Brintzinger

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.

摘要翻译： 描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底整体的保险丝组; 并且散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。 在保险丝熔断操作期间，由激光束击中的点周围的空隙作为裂纹停止，以防止对存在的相邻电路元件或其它熔断体的损坏。 通过适当地定形和定位空隙，可以获得保险丝之间更紧密的间距。

公开(公告)号：US06380003B1

公开(公告)日：2002-04-30

申请号：US09469374

申请日：1999-12-22

申请人： Christopher V. Jahnes ,  Chandrasekhar Narayan ,  Carl J. Radens

发明人： Christopher V. Jahnes ,  Chandrasekhar Narayan ,  Carl J. Radens

IPC分类号： H01L2182

CPC分类号： H01L23/5252 ,  H01L21/76816 ,  H01L2221/1057 ,  H01L2924/0002 ,  H01L2924/00

摘要： Interconnect structures comprising a substrate having a first level of electrically conductive features formed thereon; a patterned interlevel dielectric material formed on said substrate, wherein said patterned interlevel dielectric includes via spaces, wherein at least one of said via spaces is a slot via in which an anti-fuse material is formed on a portion thereof; and a second level of electrically conductive features formed in said spaces, whereby the anti-fuse material in the slot via provides a connection between the first and second levels of electrically conductive features and a method of fabricating the same.

摘要翻译： 互连结构，包括其上形成有第一层导电特征的基底; 形成在所述衬底上的图案化层间电介质材料，其中所述图案化层间电介质包括通孔空间，其中所述通孔空间中的至少一个是其中在其一部分上形成反熔丝材料的槽通孔; 以及形成在所述空间中的第二级别的导电特征，由此所述槽通孔中的所述反熔丝材料提供所述第一和第二层导电特征之间的连接及其制造方法。

公开(公告)号：US06301903B1

公开(公告)日：2001-10-16

申请号：US09495896

申请日：2000-02-02

申请人： Daniel Charles Edelstein ,  Chandrasekhar Narayan

发明人： Daniel Charles Edelstein ,  Chandrasekhar Narayan

IPC分类号： F25B1900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for activating fusible links on a circuit substrate. The circuit substrate is supported in a fixture which is cooled to a below ambient temperature. Cooling of the circuit substrate decreases the absorption of energy by the substrate, permitting a smaller spot size laser beam having a lower wavelength to be employed for interrupting the fusible links. The substrate is cooled by a refrigeration coil in heat transfer with the fixture holding the substrate. Moisture formation is avoided by placing the substrate and laser source in a controlled atmosphere.

摘要翻译： 一种用于激活电路基板上的可熔链节的方法和装置。 电路基板被支撑在被冷却到低于环境温度的固定装置中。 电路基板的冷却减少了基板的能量吸收，允许采用较低波长的较小的点尺寸的激光束来中断熔丝。 基板通过热传递的冷冻盘管冷却，夹具固定基板。 通过将基板和激光源放置在受控的气氛中来避免水分形成。

公开(公告)号：US6127721A

公开(公告)日：2000-10-03

申请号：US940807

申请日：1997-09-30

申请人： Chandrasekhar Narayan ,  Bettina Dinkel

发明人： Chandrasekhar Narayan ,  Bettina Dinkel

IPC分类号： H01L21/82 ,  H01L23/31 ,  H01L23/525 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L23/5258 ,  H01L23/3171 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/19041

摘要： The use of an etch stop layer to define a terminal via opening to access a device feature after formation of a photosensitive soft-passivation layer. The etch stop layer allows the size of the terminal via opening to be decoupled from the resolution capabilities of current photosensitive soft-passivation layer.

摘要翻译： 在形成感光软钝化层之后，使用蚀刻停止层来限定端子通孔以访问器件特征。 蚀刻停止层允许端子通孔的尺寸与当前光敏软钝化层的分辨能力分离。

公开(公告)号：US6037648A

公开(公告)日：2000-03-14

申请号：US105647

申请日：1998-06-26

申请人： Kenneth C. Arndt ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Chandrasekhar Narayan ,  Rainer F. Schnabel ,  Ronald J. Schutz ,  Dirk Tobben

发明人： Kenneth C. Arndt ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  Chandrasekhar Narayan ,  Rainer F. Schnabel ,  Ronald J. Schutz ,  Dirk Tobben

IPC分类号： H01L21/82 ,  H01L21/768 ,  H01L23/525 ,  H01L29/00

CPC分类号： H01L21/76885 ,  H01L23/5256 ,  H01L2924/0002

摘要： A semiconductor structure comprising a semiconductor substrate, an electrically conductive level on the substrate and a metal fuse located at the conductive level wherein the fuse comprises a self-aligned dielectric etch stop layer thereon is provided along with processes for its fabrication.

摘要翻译： 包括半导体衬底的半导体结构，衬底上的导电电平和位于导电水平处的金属熔断器，其中熔丝包括其上的自对准电介质蚀刻停止层以及其制造工艺。