公开(公告)号：US09947648B2

公开(公告)日：2018-04-17

申请号：US15189031

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Andreas Meiser ,  Ulrich Glaser

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L29/40 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L27/0255 ,  H01L27/06 ,  H01L27/0814 ,  H01L29/407 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/8725

Abstract: A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.

公开(公告)号：US20180019304A1

公开(公告)日：2018-01-18

申请号：US15649870

申请日：2017-07-14

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Rudolf Elpelt ,  Dethard Peters

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7813

Abstract: An embodiment of a semiconductor device includes a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type. A super junction structure is in the SiC semiconductor body, and includes a drift zone section being of the second conductivity type and a compensation structure of the first conductivity type. The compensation structure adjoins the body region and includes compensation sub-structures consecutively arranged along a vertical direction perpendicular to a surface of the SiC semiconductor body. The compensation sub-structures include a first compensation sub-structure and a second compensation sub-structure. A resistance of the second compensation sub-structure between opposite ends of the second compensation sub-structure along the vertical direction is at least five times larger than a resistance of the first compensation sub-structure between opposite ends of the first compensation sub-structure along the vertical direction.

公开(公告)号：US20180006109A1

公开(公告)日：2018-01-04

申请号：US15634720

申请日：2017-06-27

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Christian Philipp Sandow

IPC: H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H03K17/567 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7813 ,  H03K17/567

Abstract: A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.

公开(公告)号：US20170248645A1

公开(公告)日：2017-08-31

申请号：US15056111

申请日：2016-02-29

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Stefan Hain ,  Mark-Matthias Bakran

IPC: G01R31/02 ,  G01R17/00

CPC classification number: G01R31/3277 ,  G01R31/27 ,  G01R31/42 ,  H03K17/08128 ,  H03K17/0828

Abstract: Devices and methods are provided, which detect a short circuit condition related to a semiconductor switch. A short circuit condition may be determined when a control signal of the switch exceeds a first reference, and a change of load current of the switch exceeds a second reference.

公开(公告)号：US09640401B2

公开(公告)日：2017-05-02

申请号：US15188472

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Hans-Joachim Schulze ,  Anton Mauder ,  Erich Griebl

IPC: H01L21/20 ,  H01L29/739 ,  H01L21/265 ,  H01L21/02 ,  H01L21/225 ,  H01L21/306 ,  H01L21/324 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L23/544 ,  H01L21/683 ,  H01L29/861 ,  H01L21/3065

CPC classification number: H01L21/26513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/02667 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/26533 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8611 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device includes forming a cavity in a first semiconductor layer formed on a semiconducting base layer, the cavity extending from a process surface of the first semiconductor layer at least down to the base layer, forming a recessed mask liner on a portion of a sidewall of the cavity distant to the process surface or a mask plug in a portion of the cavity distant to the process surface, and growing a second semiconductor layer on the process surface by epitaxy, the second semiconductor layer spanning the cavity.

公开(公告)号：US20160380063A1

公开(公告)日：2016-12-29

申请号：US15189147

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Franz Hirler ,  Anton Mauder ,  Hermann Gruber ,  Hubert Rothleitner ,  Andreas Peter Meiser

IPC: H01L29/40

CPC classification number: H01L29/407 ,  H01L21/76224 ,  H01L21/76898 ,  H01L21/823481 ,  H01L23/481 ,  H01L24/16 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/402 ,  H01L29/408 ,  H01L29/41741 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7813 ,  H01L2224/16245 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: A method for producing a semiconductor component is provided. The method includes providing a semiconductor body with a first surface and a second surface opposite to the first surface, etching an insulation trench from the first surface partially into the semiconductor body, forming a first insulation layer on one or more sidewalls of the insulation trench, processing the second surface by at least one of grinding, polishing and a CMP-process to expose the first insulation layer, and depositing on the processed second surface a second insulation layer which extends to the first insulation layer.

Abstract translation: 提供一种半导体元件的制造方法。 该方法包括：提供具有与第一表面相对的第一表面和第二表面的半导体本体，将绝缘沟槽从第一表面部分地蚀刻到半导体本体中，在绝缘沟槽的一个或多个侧壁上形成第一绝缘层， 通过研磨，抛光和CMP工艺中的至少一个来处理第二表面以暴露第一绝缘层，以及在经处理的第二表面上沉积延伸到第一绝缘层的第二绝缘层。

公开(公告)号：US20160307885A1

公开(公告)日：2016-10-20

申请号：US15189031

申请日：2016-06-22

Applicant: Infineon Technologies AG

Inventor： Joachim Weyers ,  Anton Mauder ,  Franz Hirler ,  Andreas Meiser ,  Ulrich Glaser

IPC: H01L27/02 ,  H01L29/40 ,  H01L29/872

CPC classification number: H01L27/0255 ,  H01L27/06 ,  H01L27/0814 ,  H01L29/407 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/8725

Abstract: A semiconductor device includes a semiconductor body including a first trench extending into the semiconductor body from a first surface and a diode including an anode region and a cathode region. One of the anode region and the cathode region is at least partly arranged in the first trench. The other one of the anode region and the cathode region includes a first semiconductor region directly adjoining the one of the anode region and the cathode region from outside of the first trench, thereby constituting a pn junction. The semiconductor device further includes a conducting path through a sidewall of the first trench.

Abstract translation: 半导体器件包括半导体本体，其包括从第一表面延伸到半导体本体中的第一沟槽和包括阳极区域和阴极区域的二极管。 阳极区域和阴极区域中的一个至少部分地布置在第一沟槽中。 阳极区域和阴极区域中的另一个包括从第一沟槽的外部直接邻接阳极区域和阴极区域中的一个的第一半导体区域，从而构成pn结。 半导体器件还包括穿过第一沟槽的侧壁的导电路径。

公开(公告)号：US09385222B2

公开(公告)日：2016-07-05

申请号：US14180924

申请日：2014-02-14

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Hans-Joachim Schulze ,  Anton Mauder ,  Erich Griebl

IPC: H01L21/20 ,  H01L29/739 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L29/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66 ,  H01L21/683 ,  H01L23/544

CPC classification number: H01L21/26513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02598 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/02647 ,  H01L21/0265 ,  H01L21/02667 ,  H01L21/2251 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/26533 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/3247 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/04 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/36 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8611 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A cavity is formed in a first semiconductor layer that is formed on a semiconducting base layer. The cavity extends from a process surface of the first semiconductor layer to the base layer. A recessed mask liner is formed on a portion of a sidewall of the cavity distant to the process surface or a mask plug is formed in a portion of the cavity distant do the process surface. A second semiconductor layer is grown by epitaxy on the process surface. The second semiconductor layer spans the cavity.

Abstract translation: 在形成在半导体基底层上的第一半导体层中形成空腔。 空腔从第一半导体层的工艺表面延伸到基层。 凹陷的掩模衬垫形成在远离处理表面的空腔的侧壁的一部分上，或者在远离处理表面的空腔的一部分中形成掩模塞。 通过在工艺表面上外延生长第二半导体层。 第二半导体层跨越空腔。

公开(公告)号：US20150239363A1

公开(公告)日：2015-08-27

申请号：US14185982

申请日：2014-02-21

Applicant: Infineon Technologies AG

Inventor： Philip Georg Brockerhoff ,  Anton Mauder

IPC: B60L11/18 ,  H02J7/00

CPC classification number: B60L11/1848 ,  B60L11/1803 ,  B60L11/1805 ,  B60L11/1816 ,  B60L2240/547 ,  H02J7/0029 ,  H02J7/008 ,  H02J7/0091 ,  H02J7/1492 ,  H02J7/345 ,  H02J2007/0037 ,  H02M1/088 ,  H02M1/32 ,  H02M7/797 ,  H02M2001/348 ,  Y02T10/7005 ,  Y02T10/7072 ,  Y02T10/92 ,  Y02T90/121 ,  Y02T90/127 ,  Y02T90/128 ,  Y02T90/14 ,  Y02T90/163 ,  Y02T90/169 ,  Y04S30/14 ,  Y10S903/907

Abstract: A circuit is provided, including a battery, an omnipolar switch, a switching element, a DC-intermediate circuit and a current supplying circuit. The omnipolar switch may be coupled to the battery and may be configured to electrically disconnect the battery. The DC-intermediate circuit may be coupled to the omnipolar switch via the switching element, and the current supplying device may be coupled to the DC-intermediate circuit.

Abstract translation: 提供了一种电路，包括电池，全极性开关，开关元件，直流中间电路和电流供应电路。 全极开关可以耦合到电池并且可以被配置为电断开电池。 DC中间电路可以经由开关元件耦合到全极开关，并且电流供应装置可以耦合到DC中间电路。

公开(公告)号：US20150109050A1

公开(公告)日：2015-04-23

申请号：US14551632

申请日：2014-11-24

Applicant: Infineon Technologies AG

Inventor： Frank Pfirsch ,  Dorothea Werber ,  Anton Mauder ,  Carsten Schaeffer

IPC: H03K17/66 ,  H03K3/01 ,  H01L29/739

CPC classification number: H03K17/127 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H03K3/01 ,  H03K17/66

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract translation: 根据一种方法的实施例，半导体器件在反向偏置单极模式下工作，然后在正向偏置模式中将半导体器件操作为截止状态。 半导体器件包括设置在器件的单元区域外的至少一个浮置寄生区域。