公开(公告)号：US09368435B2

公开(公告)日：2016-06-14

申请号：US14493493

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Dominic Maier ,  Chooi Mei Chong

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L23/48 ,  H01L25/07

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/17 ,  H01L24/20 ,  H01L25/072 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/1712 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.

Abstract translation: 在一个实施例中，电子部件包括电介质层，嵌入电介质层中的半导体器件，导电衬底，具有第一表面的再分配层和提供至少一个外部触点的第二表面，以及第一导电构件 。 半导体器件具有包括至少一个第一接触焊盘的第一表面和包括至少一个第二接触焊盘的第二表面。 第二接触垫安装在导电基板上。 第一导电构件包括至少一个柱形突起并且在导电基底和再分布层的第一表面之间延伸。

公开(公告)号：US20160086876A1

公开(公告)日：2016-03-24

申请号：US14493493

申请日：2014-09-23

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Dominic Maier ,  Chooi Mei Chong

IPC: H01L23/495 ,  H01L25/07 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/481 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49575 ,  H01L23/49844 ,  H01L24/17 ,  H01L24/20 ,  H01L25/072 ,  H01L2224/0237 ,  H01L2224/04105 ,  H01L2224/16245 ,  H01L2224/1712 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/1304 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

Abstract: In an embodiment, an electronic component includes a dielectric layer, a semiconductor device embedded in the dielectric layer, an electrically conductive substrate, a redistribution layer having a first surface and a second surface providing at least one outer contact, and a first electrically conductive member. The semiconductor device has a first surface including at least one first contact pad and a second surface including at least one second contact pad. The second contact pad is mounted on the electrically conductive substrate. The first electrically conductive member includes at least one stud bump and extends between the electrically conductive substrate and the first surface of the redistribution layer.

Abstract translation: 在一个实施例中，电子部件包括电介质层，嵌入电介质层中的半导体器件，导电衬底，具有第一表面的再分配层和提供至少一个外部触点的第二表面，以及第一导电构件 。 半导体器件具有包括至少一个第一接触焊盘的第一表面和包括至少一个第二接触焊盘的第二表面。 第二接触垫安装在导电基板上。 第一导电构件包括至少一个柱形突起并且在导电基底和再分布层的第一表面之间延伸。

公开(公告)号：US09230880B2

公开(公告)日：2016-01-05

申请号：US14165754

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Teck Sim Lee ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/495 ,  H01L23/40 ,  H01L21/3105 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L23/367 ,  H01L23/433

CPC classification number: H01L23/4006 ,  H01L21/31053 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.

Abstract translation: 电子设备包括半导体芯片，其包括电极，基板元件和将电极连接到基板元件的接触元件。 电子设备还包括密封剂，其被配置为使接触元件至少部分地暴露，使得散热器可以连接到接触元件。

公开(公告)号：US09117786B2

公开(公告)日：2015-08-25

申请号：US13693205

申请日：2012-12-04

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/12 ,  H01L23/34 ,  H01L21/56 ,  H01L23/36 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/34 ,  H01L21/56 ,  H01L23/36 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/5389 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The chip module includes a carrier, a semiconductor chip arranged on or embedded inside the carrier, and an insulation layer that at least partly covers a face of the carrier. The dielectric constant ∈r and the thermal conductivity λ of the insulation layer satisfy the condition λ·∈r

Abstract translation: 芯片模块包括载体，布置在载体上或嵌入载体内部的半导体芯片，以及至少部分覆盖载体的表面的绝缘层。 绝缘层的介电常数εr和热导率λ满足条件λ·∈r<4.0 W·m-1·K-1。

公开(公告)号：US09082759B2

公开(公告)日：2015-07-14

申请号：US13686767

申请日：2012-11-27

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Fabio Brucchi

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

Abstract translation: 根据本发明的一个实施例，一种半导体封装包括一个管芯焊盘和一个设置在管芯焊盘周围的密封剂。 半导体封装具有第一侧壁和第二侧壁。 第二侧壁垂直于第一侧壁。 第一侧壁和第二侧壁限定拐角区域。 连接杆设置在密封剂内。 连接杆连接模片，并延伸离开模具桨。 在拐角区域设置虚拟引线。 虚拟引线不与半导体封装内的另一导电部件电耦合。 虚拟引线和连接杆之间的距离小于连接条与半导体封装中的其它引线或其他连接条之间的最短距离。

公开(公告)号：US20140145318A1

公开(公告)日：2014-05-29

申请号：US13686767

申请日：2012-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ralf Otremba ,  Klaus Schiess ,  Fabio Brucchi

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13062 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

Abstract translation: 根据本发明的一个实施例，一种半导体封装包括一个管芯焊盘和一个设置在管芯焊盘周围的密封剂。 半导体封装具有第一侧壁和第二侧壁。 第二侧壁垂直于第一侧壁。 第一侧壁和第二侧壁限定拐角区域。 连接杆设置在密封剂内。 连接杆连接模片，并延伸离开模具桨。 在拐角区域设置虚拟引线。 虚拟引线不与半导体封装内的另一导电部件电耦合。 虚拟引线和连接杆之间的距离小于连接条与半导体封装中的其它引线或其他连接条之间的最短距离。

公开(公告)号：US10418319B2

公开(公告)日：2019-09-17

申请号：US13893937

申请日：2013-05-14

Applicant: Infineon Technologies AG

Inventor： Oliver Haeberlen ,  Klaus Schiess ,  Stefan Kramp

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L23/14 ,  H01L23/36 ,  H01L23/492 ,  H01L23/00

Abstract: A method of manufacturing a semiconductor device includes providing an electrically conductive carrier and placing a semiconductor chip over the carrier. The method includes applying an electrically insulating layer over the carrier and the semiconductor chip. The electrically insulating layer has a first face facing the carrier and a second face opposite to the first face. The method includes selectively removing the electrically insulating layer and applying solder material where the electrically insulating layer is removed and on the second face of the electrically insulating layer.

公开(公告)号：US09812373B2

公开(公告)日：2017-11-07

申请号：US14960804

申请日：2015-12-07

Applicant: Infineon Technologies AG

Inventor： Christian Fachmann ,  Ralf Otremba ,  Klaus Schiess ,  Franz Stueckler

IPC: H01L23/367 ,  H01L23/373 ,  F28F21/08 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/3672 ,  F28F21/081 ,  H01L23/367 ,  H01L23/3735 ,  H01L23/3736 ,  H01L23/3737 ,  H01L23/49551 ,  H01L24/00 ,  H01L2224/06181 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encapsulation body, a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip, and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. The electrically insulating layer is completely separated from the semiconductor chip.

公开(公告)号：US20160064255A1

公开(公告)日：2016-03-03

申请号：US14935510

申请日：2015-11-09

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Xaver Schloegel ,  Klaus Schiess ,  Bernd Roemer ,  Edward Fuergut

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3135 ,  H01L23/34 ,  H01L23/495 ,  H01L23/49562 ,  H01L23/49568 ,  H01L23/552 ,  H01L24/05 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/13034 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099

Abstract: A method for manufacturing a chip arrangement, including disposing a chip over a carrier, wherein the bottom side of the chip is electrically connected to the first carrier side via one or more contact pads on the chip bottom side, disposing a first encapsulation material over the first carrier side, wherein the first encapsulation material at least partially surrounds the chip, and disposing a second encapsulation material over a second carrier side, wherein the second encapsulation material is in direct contact with the second carrier side.

Abstract translation: 一种用于制造芯片布置的方法，包括在载体上布置芯片，其中芯片的底侧通过芯片底侧上的一个或多个接触焊盘电连接到第一载体侧，在第一封装材料上设置第一封装材料 第一载体侧，其中第一封装材料至少部分地围绕芯片，并且在第二载体侧上设置第二封装材料，其中第二封装材料与第二载体侧直接接触。

公开(公告)号：US20150214133A1

公开(公告)日：2015-07-30

申请号：US14165754

申请日：2014-01-28

Applicant: Infineon Technologies AG

Inventor： Ralf Otremba ,  Josef Hoeglauer ,  Juergen Schredl ,  Teck Sim Lee ,  Xaver Schloegel ,  Klaus Schiess

IPC: H01L23/40 ,  H01L23/00 ,  H01L21/3105 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/4006 ,  H01L21/31053 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/367 ,  H01L23/4093 ,  H01L23/4334 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/37 ,  H01L24/40 ,  H01L24/83 ,  H01L2023/4031 ,  H01L2023/405 ,  H01L2023/4087 ,  H01L2224/37147 ,  H01L2224/3754 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.

Abstract translation: 电子设备包括半导体芯片，其包括电极，基板元件和将电极连接到基板元件的接触元件。 电子设备还包括密封剂，其被配置为使接触元件至少部分地暴露，使得散热器可以连接到接触元件。