公开(公告)号：US20150228633A1

公开(公告)日：2015-08-13

申请号：US14570570

申请日：2014-12-15

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Masud Beroz ,  Liang Wang

IPC: H01L25/16 ,  H01L33/64 ,  H01L33/62

CPC classification number: H01L25/162 ,  F21K9/23 ,  F21Y2115/10 ,  H01L21/6835 ,  H01L21/78 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/97 ,  H01L25/167 ,  H01L33/0079 ,  H01L33/62 ,  H01L33/644 ,  H01L2221/6835 ,  H01L2224/05567 ,  H01L2224/05686 ,  H01L2224/06102 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/29186 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83896 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1461 ,  Y02B20/42 ,  H01L2924/01031 ,  H01L2924/0503 ,  H01L2924/053 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05552

Abstract: Front facing piggyback wafer assembly. In accordance with an embodiment of the present invention, a plurality of piggyback substrates are attached to a carrier wafer. The plurality of piggyback substrates are dissimilar in composition to the carrier wafer. The plurality of piggyback substrates are processed, while attached to the carrier wafer, to produce a plurality of integrated circuit devices. The plurality of integrated circuit devices are singulated to form individual integrated circuit devices. The carrier wafer may be processed to form integrated circuit structures prior to the attaching.

Abstract translation: 前面的背负式晶圆组件。 根据本发明的一个实施例，多个搭载基板被附着在载体晶片上。 多个背负衬底的组成与载体晶片不同。 在附着于载体晶片的同时处理多个搭载基板以产生多个集成电路装置。 多个集成电路器件被单个化以形成单独的集成电路器件。 载体晶片可以在连接之前被处理以形成集成电路结构。

公开(公告)号：US09070849B2

公开(公告)日：2015-06-30

申请号：US14058141

申请日：2013-10-18

Applicant: Invensas Corporation

Inventor： Ilyas Mohammed ,  Liang Wang ,  Steven D. Gottke

IPC: H01L33/60 ,  H01L27/15 ,  H01L25/075 ,  H01L33/62

CPC classification number: H01L33/60 ,  F21K9/23 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/62 ,  H01L2224/48463 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/19107 ,  H01L2933/0066

Abstract: In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.

Abstract translation: 根据本发明的实施例，制品包括被配置为从多于两个表面发射光的侧面发光发光二极管。 该制品包括电和热耦合到发光二极管的第一侧的第一片，以及电耦合到发光二极管的第二侧的第二片。 制品还包括多个反射表面，其被配置为通过第一片材中的孔反射来自发光二极管的所有表面的光。 光可以通过全内反射来反射。

公开(公告)号：US20140014894A1

公开(公告)日：2014-01-16

申请号：US13732275

申请日：2012-12-31

Applicant: INVENSAS CORPORATION

Inventor： Ilyas Mohammed ,  Liang Wang

IPC: H01L33/38 ,  H01L33/06

CPC classification number: H01L33/62 ,  H01L33/06 ,  H01L33/382 ,  H01L33/42 ,  H01L33/502 ,  H01L33/58 ,  H01L33/60 ,  H01L33/644 ,  H01L33/647 ,  H01L2924/0002 ,  H01L2933/0066 ,  H01L2924/00

Abstract: High performance light emitting diode with vias. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a plurality of filled vias configured to connect a doped region on one side of the light emitting diode to a plurality of contacts on the other side of the light emitting diode. The filled vias may comprise less that 10% of a surface area of the light emitting diode.

Abstract translation: 具有通孔的高性能发光二极管。 根据本发明的第一实施例，制品包括发光二极管。 发光二极管包括多个填充的通孔，其被配置为将发光二极管的一侧上的掺杂区域连接到发光二极管的另一侧上的多个触点。 填充的通孔可以包含少于发光二极管表面积的10％。

公开(公告)号：US10586785B2

公开(公告)日：2020-03-10

申请号：US15927494

申请日：2018-03-21

Applicant: Invensas Corporation

Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

IPC: H01L25/065 ,  H01L23/36 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L25/00

Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

公开(公告)号：US10522457B2

公开(公告)日：2019-12-31

申请号：US16238786

申请日：2019-01-03

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Arkalgud R. Sitaram ,  Hong Shen ,  Zhuowen Sun ,  Liang Wang ,  Guilian Gao

IPC: H01L23/04 ,  H01L23/52 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768 ,  H01L21/8234

Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, one or more conductive features (120E.A, 120E.B, or both) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.

公开(公告)号：US10440822B2

公开(公告)日：2019-10-08

申请号：US15682049

申请日：2017-08-21

Applicant: Invensas Corporation

Inventor： Bong-Sub Lee ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Liang Wang ,  Laura Wills Mirkarimi ,  Arkalgud R. Sitaram

IPC: H05K13/04 ,  H05K1/09 ,  H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/16 ,  H05K3/18

Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130′) covered by a conductive coating (130″) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.

公开(公告)号：US20190172903A1

公开(公告)日：2019-06-06

申请号：US16272736

申请日：2019-02-11

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L49/02 ,  H01L23/00 ,  H01L21/56 ,  H01L23/522 ,  H01L25/00 ,  H01L25/16 ,  H01L25/11 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L28/60 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L25/11 ,  H01L25/115 ,  H01L25/165 ,  H01L25/50 ,  H01L28/40 ,  H01L28/65 ,  H01L2224/05009 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1205 ,  H01L2924/15311 ,  H01L2924/16153 ,  H01L2924/00

Abstract: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.

公开(公告)号：US20190148339A1

公开(公告)日：2019-05-16

申请号：US16246863

申请日：2019-01-14

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/08145 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/24145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/821 ,  H01L2224/92124 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/14 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2224/80001 ,  H01L2224/81

Abstract: Apparatuses and methods are described. This apparatus includes a bridge die having first contacts on a die surface being in a molding layer of a reconstituted wafer. The reconstituted wafer has a wafer surface including a layer surface of the molding layer and the die surface. A redistribution layer on the wafer surface includes electrically conductive and dielectric layers to provide conductive routing and conductors. The conductors extend away from the die surface and are respectively coupled to the first contacts at bottom ends thereof. At least second and third IC dies respectively having second contacts on corresponding die surfaces thereof are interconnected to the bridge die and the redistribution layer. A first portion of the second contacts are interconnected to top ends of the conductors opposite the bottom ends thereof in part for alignment of the at least second and third IC dies to the bridge die.

公开(公告)号：US20190088607A1

公开(公告)日：2019-03-21

申请号：US16196313

申请日：2018-11-20

Applicant: Invensas Corporation

Inventor： Liang Wang ,  Rajesh Katkar ,  Hong Shen

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/34 ,  H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L25/18 ,  B81B7/00 ,  H01L23/538 ,  H01L21/56 ,  H01L25/00 ,  H01L23/48 ,  H01L21/768 ,  B81C1/00

Abstract: In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.

公开(公告)号：US10204977B2

公开(公告)日：2019-02-12

申请号：US15804847

申请日：2017-11-06

Applicant: INVENSAS CORPORATION

Inventor： Liang Wang ,  Hong Shen ,  Rajesh Katkar

IPC: H01L21/56 ,  H01L49/02 ,  H01L23/00 ,  H01L25/10 ,  H01L25/11 ,  H01L25/16 ,  H01L25/00 ,  H01L23/498 ,  H01L23/522

Abstract: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.