公开(公告)号：US20240071848A1

公开(公告)日：2024-02-29

申请号：US17895916

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Bai NIE ,  Gang DUAN ,  Kyle ARRINGTON ,  Ziyin LIN ,  Hongxia FENG ,  Yiqun BAI ,  Xiaoying GUO ,  Dingying David XU ,  Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD

IPC: H01L23/15 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827

Abstract: Embodiments disclosed herein include package substrates. In an embodiment, the package substrate comprises a core, where the core comprises glass. In an embodiment, a first layer is under the core, a second layer is over the core, and a via is through the core, the first layer, and the second layer. In an embodiment a width of the via through the core is equal to a width of the via through the first layer and the second layer. In an embodiment, the package substrate further comprises a first pad under the via, and a second pad over the via.

公开(公告)号：US20240063203A1

公开(公告)日：2024-02-22

申请号：US17889962

申请日：2022-08-17

Applicant: Intel Corporation

Inventor： Brandon C. MARIN ,  Ravindranath V. MAHAJAN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD ,  Jeremy D. ECTON ,  Navneet SINGH ,  Sushil PADMANABHAN ,  Samarth ALVA

IPC: H01L25/18 ,  H01L23/15 ,  H01L23/538 ,  H01L23/48 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/18 ,  H01L23/15 ,  H01L23/5383 ,  H01L23/481 ,  H01L23/5384 ,  H01L21/486 ,  H01L21/4857 ,  H01L25/50 ,  H01L21/56

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass, and buildup layers over the first substrate. In an embodiment, a first die is over the buildup layers, a second die is over the buildup layers and adjacent to the first die, and where conductive routing in the buildup layers electrically couples the first die to the second die.

公开(公告)号：US20240063127A1

公开(公告)日：2024-02-22

申请号：US17889238

申请日：2022-08-16

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Suddhasattwa NAD

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/13 ,  H01L23/15 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/13 ,  H01L23/15 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0652 ,  H01L2924/1511 ,  H01L2924/15153 ,  H01L2924/152 ,  H01L2924/15788 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first substrate with a cavity, where the first substrate comprises glass. In an embodiment, a second substrate is in the cavity. In an embodiment, a bond film covers a bottom of the second substrate and extends up sidewalls of the second substrate.

公开(公告)号：US20230207503A1

公开(公告)日：2023-06-29

申请号：US17561824

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Jieying KONG ,  Bainye Francoise ANGOUA ,  Dilan SENEVIRATNE ,  Whitney M. BRYKS ,  Jeremy D. ECTON

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/34 ,  H01L2224/73265 ,  H01L2924/186 ,  H01L2924/01029

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate. The metallic contact has a contact surface to make electrical contact with a trace through a dielectric layer over the semiconductor circuit substrate and the metallic contact. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The metallic contact includes a vertical lip extending vertically into the dielectric layer above the contact surface.

公开(公告)号：US20230137877A1

公开(公告)日：2023-05-04

申请号：US17517152

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Haobo CHEN ,  Omkar KARHADE ,  Malavarayan SANKARASUBRAMANIAN ,  Dingying XU ,  Gang DUAN ,  Bai NIE ,  Xiaoying GUO ,  Kristof DARMAWIKARTA ,  Hongxia FENG ,  Srinivas PIETAMBARAM ,  Jeremy D. ECTON

IPC: H01L23/00 ,  H01L25/065

Abstract: No-remelt solder joints can eliminate die or substrate movement in downstream reflow processes. In one example, one or more solder joints between two substrates can be formed as full IMC (intermetallic compound) solder joints. In one example, a full IMC solder joint includes a continuous layer (e.g., from the top pad to bottom pad) of intermetallic compounds. In one example, a full IMC joint can be formed by dispensing a no-remelt solder paste on some of the pads of one or both substrates to be bonded together.

公开(公告)号：US20230087810A1

公开(公告)日：2023-03-23

申请号：US17482852

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Jeremy D. ECTON ,  Kristof DARMAWIKARTA ,  Suddhasattwa NAD ,  Oscar OJEDA ,  Bai NIE ,  Brandon C. MARIN ,  Gang DUAN ,  Jacob VEHONSKY ,  Onur OZKAN ,  Nicholas S. HAEHN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a plurality of stacked layers. In an embodiment, a first trace is on a first layer, wherein the first trace has a first thickness. In an embodiment, a second trace is on the first layer, wherein the second trace has a second thickness that is greater than the first thickness. In an embodiment, a second layer is over the first trace and the second trace.

公开(公告)号：US20250106983A1

公开(公告)日：2025-03-27

申请号：US18373457

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Kyle ARRINGTON ,  Dingying David XU ,  Ziyin LIN ,  Timothy GOSSELIN ,  Elah BOZORG-GRAYELI ,  Aravindha ANTONISWAMY ,  Wei LI ,  Haobo CHEN ,  Yiqun BAI ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Ashay DANI

IPC: H05K1/02 ,  H05K1/03

Abstract: Embodiments disclosed herein include glass core package substrates with a stiffener. In an embodiment, an apparatus comprises a substrate with a first layer with a first width, where the first layer is a glass layer, a second layer under the first layer, where the second layer has a second width that is smaller than the first width, and a third layer over the first layer, where the third layer has a third width that is smaller than the first width. In an embodiment, the apparatus further comprises a metallic structure with a first portion and a second portion, where the first portion is over a top surface of the substrate and the second portion extends away from the first portion and covers at least a sidewall of the first layer.

公开(公告)号：US20240222130A1

公开(公告)日：2024-07-04

申请号：US18091026

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Shaojiang CHEN ,  Jeremy D. ECTON ,  Oladeji FADAYOMI ,  Hsin-Wei WANG ,  Changhua LIU ,  Bin MU ,  Hongxia FENG ,  Brandon C. MARIN ,  Srinivas V. PIETAMBARAM

IPC: H01L21/306 ,  H01L21/321 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/30604 ,  H01L21/3212 ,  H01L21/486 ,  H01L21/7688 ,  H01L21/76898 ,  H01L21/268

Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises a core, where the core comprises glass. In an embodiment, a through glass via (TGV) is provided through a thickness of the core. In an embodiment, the TGV comprises a top surface that is non-planar and includes a symmetric ridge on the non-planar top surface.

公开(公告)号：US20240213111A1

公开(公告)日：2024-06-27

申请号：US18088360

申请日：2022-12-23

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Je-Young CHANG ,  Jeremy D. ECTON ,  Rahul N. MANEPALLI ,  Srinivas V. PIETAMBARAM ,  Gang DUAN ,  Brandon C. MARIN ,  Suddhasattwa NAD

IPC: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/498

CPC classification number: H01L23/367 ,  G06F1/20 ,  H01L23/15 ,  H01L23/427 ,  H01L23/473 ,  H01L23/49816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a core with a first surface and a second surface opposite from the first surface, and where the core comprises glass. In an embodiment, a channel is disposed into the first surface of the core, and a lid is provided over the channel. In an embodiment, the lid seals the channel between a first end and a second end of the channel.

公开(公告)号：US20240178119A1

公开(公告)日：2024-05-30

申请号：US18071116

申请日：2022-11-29

Applicant: Intel Corporation

Inventor： Mohammad Mamunur RAHMAN ,  Jeremy D. ECTON ,  Gang DUAN

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/15 ,  H01L23/538

CPC classification number: H01L23/49838 ,  H01L23/13 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49866 ,  H01L23/5381 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/5385 ,  H01L2224/13111 ,  H01L2224/1601 ,  H01L2224/16055 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17055 ,  H01L2224/17152 ,  H01L2224/17153 ,  H01L2924/37001

Abstract: Embodiments disclosed herein include an interconnect. In an embodiment, the interconnect comprises a substrate and a pad over the substrate. In an embodiment, a hole is provided through the pad. In an embodiment, the hole exposes a portion of the substrate. In an embodiment, a solder is provided over the pad, and the solder bridges across the hole through the pad.