公开(公告)号：US10522453B2

公开(公告)日：2019-12-31

申请号：US15352856

申请日：2016-11-16

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chun-Tang Lin ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

Abstract: Provided is a substrate structure including a substrate body, electrical contact pads and an insulating protection layer disposed on the substrate body, wherein the insulating protection layer has openings exposing the electrical contact pads, and at least one of the electrical contact pads has at least a concave portion filled with a filling material to prevent solder material from permeating along surfaces of the insulating protection layer and the electric contact pads, thereby eliminating the phenomenon of solder extrusion. Thus, bridging in the substrate structure can be eliminated even when the bump pitch between two adjacent electrical contact pads is small. As a result, short circuits can be prevented, and production yield can be increased.

公开(公告)号：US10510720B2

公开(公告)日：2019-12-17

申请号：US15372638

申请日：2016-12-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Kuo-Hua Yu ,  Fu-Tang Huang

IPC: H01L23/31 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

Abstract: An electronic package is provided, which includes: a first substrate; a first electronic component disposed on the first substrate; a second substrate stacked on the first substrate through a plurality of first conductive elements and a plurality of second conductive elements and bonded to the first electronic component through a bonding layer; and a first encapsulant formed between the first substrate and the second substrate. The first conductive elements are different in structure from the second conductive elements so as to prevent a mold flow of the first encapsulant from generating an upward pushing force during a molding process and hence avoid cracking of the second substrate. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09842771B2

公开(公告)日：2017-12-12

申请号：US14272764

申请日：2014-05-08

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Hung-Ming Chang ,  Ming-Chin Chuang ,  Fu-Tang Huang

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L21/76895 ,  H01L21/563 ,  H01L23/3171 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/034 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/206 ,  H01L2924/207 ,  H01L2924/014

Abstract: A semiconductor device is disclosed, which includes: a substrate having a plurality of connecting pads; a semiconductor component having a plurality of bonding pads formed on a surface thereof and corresponding to the connecting pads and a UBM layer formed on the bonding pads; a plurality of conductive elements each having a first conductive portion and a second conductive portion sequentially formed on the UBM layer, wherein the second conductive portion is less in width than the first conductive portion; and a plurality of solder balls formed between the second conductive portions and the connecting pads for connecting the semiconductor component and the substrate, thereby preventing solder bridging from occurring between the adjacent conductive elements and reducing stresses between the conductive elements and the UBM layer.

公开(公告)号：US09368467B2

公开(公告)日：2016-06-14

申请号：US13654713

申请日：2012-10-18

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/498 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/00014 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.

Abstract translation: 提供了一种基板结构，包括基板主体和形成在基板主体上的多个电路。 至少一个电路具有用于连接到外部元件的电触点，并且电触头的宽度比电路窄，从而满足细线/细间距和小型化的要求，提高产品产量并降低制造成本 。

公开(公告)号：US20150332998A1

公开(公告)日：2015-11-19

申请号：US14564145

申请日：2014-12-09

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC: H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49822 ,  H01L23/3121 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15174 ,  H01L2924/181 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0195 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.

Abstract translation: 提供了一种封装基板和封装结构。 包装衬底包括多个电介质层，其中两个具有不同的厚度; 以及与电介质层交替层叠的多个电路层。 因此，避免了现有技术中遇到的包装翘曲。

公开(公告)号：US20150004752A1

公开(公告)日：2015-01-01

申请号：US14085959

申请日：2013-11-21

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Keng-Hung Liu ,  Fu-Tang Huang

IPC: H01L21/78 ,  H01L23/544

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L23/3178 ,  H01L23/544 ,  H01L24/06 ,  H01L24/17 ,  H01L2223/54453 ,  H01L2224/0401 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/15311 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00

Abstract: A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner; a stopping portion formed at edges of the semiconductor element; an insulating layer formed on an active surface of the semiconductor element and the stopping portion; and an encapsulant formed between the packaging substrate and the insulating layer. The insulating layer has a recessed portion formed on the stopping portion and facing the packaging substrate such that during a reliability test, the recessed portion can prevent delamination occurring between the insulating layer and the stopping portion from extending to the active surface of the semiconductor element.

Abstract translation: 公开了一种半导体封装，其包括：封装基板; 以倒装芯片的方式设置在封装衬底上的半导体元件; 形成在所述半导体元件的边缘处的止动部; 绝缘层，形成在所述半导体元件的有源表面和所述止动部分上; 以及形成在包装基板和绝缘层之间的密封剂。 绝缘层具有形成在止动部分上并面向封装基板的凹陷部分，使得在可靠性测试期间，凹陷部分可以防止绝缘层和止动部分之间的分层延伸到半导体元件的有源表面。

公开(公告)号：US20140227830A1

公开(公告)日：2014-08-14

申请号：US14253324

申请日：2014-04-15

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chin-Tsai Yao ,  Chien-Ping Huang ,  Chun-Chi Ke

IPC: H01L23/00

CPC classification number: H01L24/96 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49548 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

Abstract translation: 提出了一种具有电磁干扰（EMI）屏蔽功能的四边形扁平非引线（QFN）封装结构，包括：具有管芯焊盘的引线框架，连接到管芯焊盘的多个支撑部分和围绕 裸片焊盘的周边不连接到管芯焊盘; 安装在芯片焊盘上的芯片; 电连接芯片和引线的接合线; 用于封装芯片，接合线和引线框架并暴露引线的侧表面和底表面以及管芯焊盘的底表面的密封剂; 以及屏蔽膜，其设置在密封剂的顶表面和侧表面上，并且电连接到用于屏蔽EMI的支撑部分。 进一步提出如上所述的制造封装结构的方法。

公开(公告)号：US20140061928A1

公开(公告)日：2014-03-06

申请号：US13677861

申请日：2012-11-15

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao ,  Jui-Chung Ho ,  Ching-Hui Hung

IPC: H01L23/532

CPC classification number: H01L23/53204 ,  H01L24/00 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05584 ,  H01L2224/05616 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/16503 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2924/3651 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029

Abstract: An interconnection structure for being formed on bonding pads of a substrate in a semiconductor package is provided. The interconnection structure includes a nickel layer formed on each of the bonding pads, a metal layer formed on the nickel layer, and a solder material formed on the metal layer. The metal layer is made of one of gold, silver, lead and copper, and has a thickness in the range of 0.5 to 5 um. As such, when the solder material is reflowed to form solder bumps, no nickel-tin compound is formed between the solder bumps and the metal layer, thereby avoiding cracking or delamination of the solder bumps.

Abstract translation: 提供了用于形成在半导体封装中的衬底的焊盘上的互连结构。 互连结构包括形成在每个接合焊盘上的镍层，形成在镍层上的金属层和形成在金属层上的焊料材料。 金属层由金，银，铅和铜之一制成，厚度为0.5〜5μm。 因此，当焊料材料回流以形成焊料凸块时，在焊料凸块和金属层之间不形成镍锡化合物，从而避免焊料凸块的开裂或分层。

公开(公告)号：US20130341806A1

公开(公告)日：2013-12-26

申请号：US13654713

申请日：2012-10-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H05K1/00 ,  H01L23/488

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/00014 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.

Abstract translation: 提供了一种基板结构，包括基板主体和形成在基板主体上的多个电路。 至少一个电路具有用于连接到外部元件的电触点，并且电触头的宽度比电路窄，从而满足细线/细间距和小型化的要求，提高产品产量并降低制造成本 。