公开(公告)号：US09640683B2

公开(公告)日：2017-05-02

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0203 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09570398B2

公开(公告)日：2017-02-14

申请号：US13895219

申请日：2013-05-15

Applicant: XINTEC INC.

Inventor： Shu-Ming Chang ,  Yu-Ting Huang ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L23/538 ,  H01L21/78 ,  H01L23/48 ,  B81B7/00 ,  H01L23/00 ,  H01L21/683 ,  H01L23/60

CPC classification number: H01L23/5384 ,  B81B7/007 ,  B81B2207/095 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/481 ,  H01L23/60 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/80 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05617 ,  H01L2224/05624 ,  H01L2224/08147 ,  H01L2224/08148 ,  H01L2224/13021 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/10155 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01032 ,  H01L2224/80 ,  H01L2224/83 ,  H01L21/304 ,  H01L21/76898 ,  H01L2221/68304 ,  H01L2224/0231 ,  H01L2224/11

Abstract: An embodiment of the invention provides a chip package which includes: a first substrate; a second substrate disposed thereon, wherein the second substrate includes a lower semiconductor layer, an upper semiconductor layer, and an insulating layer therebetween, and a portion of the lower semiconductor layer electrically contacts with at least one pad on the first substrate; a conducting layer disposed on the upper semiconductor layer of the second substrate and electrically connected to the portion of the lower semiconductor layer electrically contacting with the at least one pad; an opening extending from the upper semiconductor layer towards the lower semiconductor layer and extending into the lower semiconductor layer; and a protection layer disposed on the upper semiconductor layer and the conducting layer, wherein the protection layer extends onto a portion of a sidewall of the opening, and does not cover the lower semiconductor layer in the opening.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：第一基板; 设置在其上的第二基板，其中所述第二基板包括下半导体层，上半导体层和绝缘层，并且所述下半导体层的一部分与所述第一基板上的至少一个焊盘电接触; 导电层，其设置在所述第二基板的所述上半导体层上并电连接到所述下半导体层与所述至少一个焊盘电接触的部分; 从上半导体层向下半导体层延伸并延伸到下半导体层的开口; 以及设置在所述上​​半导体层和所述导电层上的保护层，其中所述保护层延伸到所述开口的侧壁的一部分上，并且不覆盖所述开口中的下半导体层。

公开(公告)号：US09559001B2

公开(公告)日：2017-01-31

申请号：US13024156

申请日：2011-02-09

Applicant: Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

Inventor： Yu-Lin Yen ,  Ming-Kun Yang ,  Tsang-Yu Liu ,  Long-Sheng Yeou

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763 ,  H01L23/58 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L2224/0501 ,  H01L2224/0557 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/00 ,  H01L2224/05552

Abstract: According to an embodiment of the invention, a chip package is provided, which includes: a substrate having an upper surface and a lower surface; a hole extending from the upper surface toward the lower surface; an insulating layer located overlying a sidewall of the hole; and a material layer located overlying the sidewall of the hole, wherein the material layer is separated from the upper surface of the substrate by a distance and a thickness of the material layer decreases along a direction toward the lower surface.

Abstract translation: 根据本发明的实施例，提供了一种芯片封装，其包括：具有上表面和下表面的基板; 从上表面向下表面延伸的孔; 位于所述孔的侧壁上方的绝缘层; 以及位于所述孔的侧壁上方的材料层，其中所述材料层与所述基板的上表面分离一定距离，并且所述材料层的厚度沿着朝向所述下表面的方向减小。

公开(公告)号：US09403672B2

公开(公告)日：2016-08-02

申请号：US14819174

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Chien-Min Lin

IPC: B81B7/00 ,  H01L21/48 ,  B81C1/00 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81B7/0058 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2207/096 ,  B81C1/00301 ,  B81C1/00682 ,  B81C2203/0118 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a bump on a lower surface of an interposer. A first insulation layer is formed to cover the lower surface and bump. A trench is formed extending from the lower towards an upper surface of the interposer. A polymer supporting adhesive layer is formed to surround the bump and couples between the interposer and a semiconductor chip. The semiconductor chip has at least a sensing component and a conductive pad electrically connected to the sensing component, and the bump is connected to the conductive pad. A via is formed extending from the upper towards the lower surface. A second insulation layer is formed to cover the upper surface and the via. A redistribution layer is formed on the second insulation layer and in the via. A packaging layer is formed to cover the redistribution layer and has a second opening.

Abstract translation: 一种方法包括在插入器的下表面上形成凸块。 形成第一绝缘层以覆盖下表面和凸起。 形成从插入件的下表面延伸到上表面的沟槽。 形成聚合物支持粘合剂层以围绕凸起并且在插入器和半导体芯片之间耦合。 半导体芯片具有至少一个感测部件和电连接到感测部件的导电焊盘，并且凸块连接到导电焊盘。 通孔形成为从上部向下表面延伸。 形成第二绝缘层以覆盖上表面和通孔。 在第二绝缘层和通孔中形成再分布层。 形成包装层以覆盖再分布层并具有第二开口。

公开(公告)号：US09397138B2

公开(公告)日：2016-07-19

申请号：US14613231

申请日：2015-02-03

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu

IPC: H01L27/146

CPC classification number: H01L27/14685 ,  H01L27/14618 ,  H01L27/14687 ,  H01L2224/11

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A carrier and a dam element are provided, and the dam element is adhered to the carrier by a temporary bonding layer. The dam element is bonded on the wafer. A first isolation layer, a redistribution layer, a second isolation layer, and a conductive structure are formed on the wafer in sequence. The carrier, the dam element and the wafer are diced to form a semiconductor element. The semiconductor element is disposed on a printed circuit board, such that the conductive structure is electrically connected to the printed circuit board. An adhesion force of the temporary bonding layer is eliminated to remove the carrier. A lens assembly is disposed on the printed circuit board, such that the semiconductor element without the carrier is located in the lens assembly.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了载体和坝元件，并且坝元件通过临时粘合层粘附到载体上。 坝体结合在晶片上。 在晶片上依次形成第一隔离层，再分配层，第二隔离层和导电结构。 将载体，坝元件和晶片切割成半导体元件。 半导体元件设置在印刷电路板上，使得导电结构电连接到印刷电路板。 消除了临时粘合层的粘合力以除去载体。 透镜组件设置在印刷电路板上，使得没有载体的半导体元件位于透镜组件中。

公开(公告)号：US09379072B2

公开(公告)日：2016-06-28

申请号：US14552186

申请日：2014-11-24

Applicant: XINTEC INC.

Inventor： Chien-Hung Liu ,  Ying-Nan Wen

IPC: H01L31/00 ,  H01L23/00 ,  H01L25/00 ,  H01L27/146

CPC classification number: H01L24/09 ,  H01L21/76898 ,  H01L24/05 ,  H01L24/13 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/1469 ,  H01L2224/02371 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/24051 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/8203 ,  H01L2224/8385 ,  H01L2224/92133 ,  H01L2224/92144 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14335 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01013 ,  H01L2924/01079 ,  H01L2924/01078 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A chip package including a first substrate is provided. A plurality of first conductive pads is disposed on a first side of the first substrate. A second substrate is attached onto a second side opposite to the first side of the first substrate. The second substrate includes a micro-electric element and has a plurality of second conductive pads corresponding to the plurality of first conductive pads, disposed on a first side of the second substrate and between the first substrate and the second substrate. A redistribution layer is disposed on a second side opposite to the first side of the second substrate. The redistribution layer penetrates the second substrate, second conductive pads and the first substrate and extends into the first conductive pads to electrically connect the first and second conductive pads.

Abstract translation: 提供了包括第一基板的芯片封装。 多个第一导电焊盘设置在第一基板的第一侧上。 第二基板附接到与第一基板的第一侧相对的第二侧。 第二基板包括微电元件，并且具有多个与多个第一导电焊盘相对应的第二导电焊盘，该第二导电焊盘设置在第二基板的第一侧上且位于第一基板和第二基板之间。 再分配层设置在与第二基板的第一侧相对的第二侧上。 再分配层穿透第二基板，第二导电焊盘和第一基板并延伸到第一导电焊盘中以电连接第一和第二导电焊盘。

公开(公告)号：US09334156B2

公开(公告)日：2016-05-10

申请号：US14747507

申请日：2015-06-23

Applicant: XINTEC INC.

Inventor： Chien-Min Lin ,  Yu-Ting Huang ,  Chen-Ning Fu ,  Yen-Shih Ho

IPC: B81B7/00 ,  B81C1/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: B81B7/007 ,  B81C1/00182 ,  B81C1/00269 ,  B81C2201/0197 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A chip package includes a semiconductor chip, an interposer, a polymer adhesive supporting layer, a redistribution layer and a packaging layer. The semiconductor chip has a sensor device and a conductive pad electrically connected to the sensing device, and the interposer is disposed on the semiconductor chip. The interposer has a trench and a through hole, which the trench exposes a portion of the sensing device, and the through hole exposes the conductive pad. The polymer adhesive supporting layer is interposed between the semiconductor chip and the interposer, and the redistribution layer is disposed on the interposer and in the through hole to be electrically connected to the conductive pad. The packaging layer covers the interposer and the redistribution layer, which the packaging layer has an opening exposing the trench.

Abstract translation: 芯片封装包括半导体芯片，插入件，聚合物粘合剂支撑层，再分布层和包装层。 半导体芯片具有传感器装置和与感测装置电连接的导电焊盘，并且插入器设置在半导体芯片上。 插入器具有沟槽和通孔，沟槽暴露感测装置的一部分，并且通孔暴露导电垫。 聚合物粘合剂支撑层插入在半导体芯片和插入件之间，并且再分配层设置在插入件上和通孔中以与导电焊盘电连接。 包装层覆盖插入件和再分配层，其中封装层具有露出沟槽的开口。

公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09209124B2

公开(公告)日：2015-12-08

申请号：US13964999

申请日：2013-08-12

Applicant: XINTEC INC.

Inventor： Yu-Lung Huang ,  Chao-Yen Lin ,  Wei-Luen Suen ,  Chien-Hui Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/58 ,  H01L23/525 ,  H01L29/06 ,  H01L21/683

CPC classification number: H01L23/585 ,  H01L21/283 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/768 ,  H01L21/78 ,  H01L23/3121 ,  H01L23/49838 ,  H01L23/525 ,  H01L24/05 ,  H01L24/16 ,  H01L24/48 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/1302 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10155 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2224/03 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: An embodiment of the invention provides a chip package including a semiconductor substrate having a first surface and a second surface opposite thereto. A conducting pad is located on the first surface. A side recess is on at least a first side of the semiconductor substrate, wherein the side recess extends from the first surface toward the second surface and across the entire length of the first side. A conducting layer is located on the first surface and electrically connected to the conducting pad, wherein the conducting layer extends to the side recess.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括具有第一表面和与其相对的第二表面的半导体衬底。 导电垫位于第一表面上。 侧凹部位于半导体衬底的至少第一侧上，其中侧凹部从第一表面朝向第二表面延伸并跨越第一侧的整个长度。 导电层位于第一表面上并电连接到导电焊盘，其中导电层延伸到侧凹槽。

公开(公告)号：US09177862B2

公开(公告)日：2015-11-03

申请号：US13727976

申请日：2012-12-27

Applicant: Xintec Inc.

Inventor： Yen-Shih Ho ,  Hsin Kuan ,  Long-Sheng Yeou ,  Tsang-Yu Liu ,  Chia-Ming Cheng

IPC: H01L21/56 ,  H01L23/498 ,  H01L21/78 ,  H01L23/48 ,  H01L23/28 ,  H01L21/82 ,  H01L23/14 ,  H01L21/683 ,  H01L21/768 ,  B81B7/00 ,  H01L23/00

CPC classification number: H01L21/82 ,  B81B7/007 ,  B81B2207/096 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/14 ,  H01L23/147 ,  H01L24/08 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L2221/68304 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2221/68368 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/24011 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/80006 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/1461 ,  H01L2224/82 ,  H01L2224/80 ,  H01L21/78

Abstract: A fabrication method of a semiconductor stack structure mainly includes: singulating a wafer of a first specification into a plurality of chips; rearranging the chips into a second specification of a wafer so as to stack the chips on a substrate of the second specification through a plurality of blocks; forming a redistribution layer on the chips; and performing a cutting process to obtain a plurality of semiconductor stack structures. Therefore, the present invention allows a wafer of a new specification to be processed by using conventional equipment without the need of new factory buildings or equipment. As such, chip packages can be timely supplied to meet the replacement speed of electronic products.

Abstract translation: 半导体堆叠结构的制造方法主要包括：将第一规格的晶片分割成多个芯片; 将芯片重新排列成晶片的第二规格，以通过多个块将芯片堆叠在第二规格的基板上; 在芯片上形成再分配层; 并执行切割处理以获得多个半导体堆叠结构。 因此，本发明允许通过使用常规设备来处理新规格的晶片，而不需要新的工厂建筑物或设备。 因此，可以及时提供芯片封装以满足电子产品的更换速度。